[U-Boot] [GIT PULL] Xilinx changes for v2018.11-rc2

[Michal Simek <michal.simek@xilinx.com>]

Hi Tom,

On 16. 10. 18 17:04, Michal Simek wrote:
> On 16.10.2018 15:38, Tom Rini wrote:
>> On Tue, Oct 16, 2018 at 10:32:14AM +0200, Michal Simek wrote:
>>> On 16.10.2018 02:32, Tom Rini wrote:
>>>> On Mon, Oct 15, 2018 at 04:25:01PM +0200, Michal Simek wrote:
>>>>
>>>>> Hi Tom,
>>>>>
>>>>> please consider to pull these patches to your tree.
>>>>> Buildmain for xilinx boards looks good and travis is not done yet but
>>>>> link is here (I have seen several timeouts recently but it was there
>>>>> even on clear mainline).
>>>>> https://travis-ci.org/michalsimek/u-boot/builds/441591781
>>>>>
>>>>> If you don't like this please at least cherry-pick this one
>>>>> Revert "fdt: fdtdec_setup_memory_banksize() use livetree"
>>>>> (sha1: 01ac0843aeedc3c95fe68e7ce6a8f35bf1a04b23)
>>>>> which I need for getting SPL up and running again on zynq/zynqmp boards.
>>>>>
>>>>> Thanks,
>>>>> Michal
>>>>>
>>>>> The following changes since commit 15f22ac2eea5ee9f17b14a143c94e7480bbafbff:
>>>>>
>>>>>   ldpaa_eth.c: Fix warning when PHYLIB is not enabled (2018-10-12
>>>>> 07:41:24 -0400)
>>>>>
>>>>> are available in the git repository at:
>>>>>
>>>>>   git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.11-rc2
>>>>>
>>>>> for you to fetch changes up to 045c62be10d64a558f56febcaa2d01b1abbcfa00:
>>>>>
>>>>>   cmd: kgdb: Enable kgdb only for PPC (2018-10-15 12:36:37 +0200)
>>>>>
>>>>
>>>> NAK.  As this stands it breaks qemu_arm running the test.py code due to:
>>>> commit 6d213c125c45db9c9d4dde5348d6e002c9f58909
>>>> Author: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
>>>> Date:   Mon Jan 22 17:49:37 2018 +0530
>>>>
>>>>     serial: pl01x: Get clock from clock node if no clock property found
>>>>
>>>>     This patch gets clock from clock nodes if no clock property found
>>>>     in serial node.
>>>>
>>>>     Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
>>>>     Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>>>
>>> I have debugged it more and the patch is good but information coming
>>> from qemu are not correct for u-boot.
>>>
>>> What it is happening for arm case is that qemu passing DT which contains
>>> these 2 fragments:
>>>
>>> 	pl011 at 9000000 {
>>> 		clock-names = "uartclk", "apb_pclk";
>>> 		clocks = <0x00008000 0x00008000>;
>>> 		interrupts = <0x00000000 0x00000001 0x00000004>;
>>> 		reg = <0x00000000 0x09000000 0x00000000 0x00001000>;
>>> 		compatible = "arm,pl011", "arm,primecell";
>>> 	};
>>>
>>> 	apb-pclk {
>>> 		phandle = <0x00008000>;
>>> 		clock-output-names = "clk24mhz";
>>> 		clock-frequency = <0x016e3600>;
>>> 		#clock-cells = <0x00000000>;
>>> 		compatible = "fixed-clock";
>>> 	};
>>>
>>> That means that when this patch is applied new code is taken because
>>> plat->clock = dev_read_u32_default(dev, "clock", 1);
>>> is returning default value 1.
>>> (I see clock property used by hi6220 which should be out of DT binding)
>>>
>>> Then clocks are taken and we get to apb-pclk which is fixed clock but it
>>> is missing "u-boot,dm-pre-reloc" property to get it work. (In connection
>>> to that CONFIG_CLK should be enabled for qemu_arm_defconfig).
>>>
>>> Just a summary of this is that it requires updating qemu by
>>> 1. adding non standard "clock" property to qemu hw/arm/virt.c
>>> or
>>> 2. by enabling CONFIG_CLK(easy) and again adding "u-boot,dm-pre-reloc"
>>> to qemu hw/arm/virt.c
>>>
>>> As is visible this requires qemu updates to get this work.
>>>
>>> Can you please tell me which way you want to go?
>>
>> I think we need a 3rd option as I can't see upstream qemu accepting a
>> U-Boot specific U-Boot property, and it'll create a bit of a support
>> nightmare too.
> 
> Good. I want to also wired Versal ASAP when qemu patches reach mainline
> to make sure that we have good coverage from the beginning that's why
> having 3rd option with different qemu HEAD would be good.
> 
> And as the part of Versal qemu upstreaming we have added u-boot property
> and will see how it goes.

I have an updated on this thread. Xilinx Versal was merged to mainline
qemu and even with u-boot,dm-pre-reloc property.
https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal-virt.c#L88

It means there shouldn't be a problem to add the same property to
hw/arm/virt.c.

Thanks,
Michal