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From: BALATON Zoltan <balaton@eik.bme.hu>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: Alexander Graf <agraf@suse.de>,
	David Gibson <david@gibson.dropbear.id.au>,
	Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: [Qemu-devel] [PATCH v6 5/5] target/ppc: Relax reserved bitmask of indexed store instructions
Date: Fri, 29 Jun 2018 00:38:33 +0200	[thread overview]
Message-ID: <bf4086546f08124e57b9676e6c0b81386ee59b67.1530225513.git.balaton@eik.bme.hu> (raw)
In-Reply-To: <cover.1530225513.git.balaton@eik.bme.hu>

The PPC440 User Manual says that if bit 31 is set, the contents of
CR[CR0] are undefined for indexed store instructions but this form is
not invalid. Other PPC variants confirming to recent ISA where this
bit may be reserved should ignore reserved bits and not raise invalid
instruction exception. In particular, MorphOS has an stwx instruction
with bit 31 set and fails to boot currently because of this. With this
patch it gets further.

---
On sam460ex MorhpOS still has problems accessing PCI devices so cannot
yet boot but does not hit the invalid instruction exception and gets
further and fails due to not finding boot volume or display controller.
On mac99 it actually boots but needs an OpenBIOS patch to get USB
working (needed for mouse and keyboard). I'll prepare some docs on how
to run different guests but for the impatient here's a little hint:
-M mac99 -m 512 -vga none -device sm501 \
-prom-env 'boot-device=cd:,\mac_ppc32\boot.img'

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 target/ppc/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3a215a1..525d55e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6886,7 +6886,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
 #define GEN_STUX(name, stop, opc2, opc3, type)                                \
 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk)                   \
-GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
+GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
 #define GEN_STS(name, stop, op, type)                                         \
 GEN_ST(name, stop, op | 0x20, type)                                           \
 GEN_STU(name, stop, op | 0x21, type)                                          \
-- 
2.7.6

  parent reply	other threads:[~2018-06-28 23:09 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-28 22:38 [Qemu-devel] [PATCH v6 0/5] Misc sam460ex improvements BALATON Zoltan
2018-06-28 22:38 ` [Qemu-devel] [PATCH v6 3/5] sam460ex: Add RTC device BALATON Zoltan
2018-06-29  4:47   ` David Gibson
2018-07-02  4:04     ` David Gibson
2018-06-28 22:38 ` [Qemu-devel] [PATCH v6 2/5] hw/timer: Add basic M41T80 emulation BALATON Zoltan
2018-06-28 22:38 ` BALATON Zoltan [this message]
2018-07-03  1:13   ` [Qemu-devel] [Qemu-ppc] [PATCH v6 5/5] target/ppc: Relax reserved bitmask of indexed store instructions David Gibson
2018-06-28 22:38 ` [Qemu-devel] [PATCH v6 4/5] ppc440_uc: Basic emulation of PPC440 DMA controller BALATON Zoltan
2018-06-29  4:48   ` David Gibson
2018-06-29  4:59     ` David Gibson
2018-06-29 12:14       ` [Qemu-devel] [Qemu-ppc] " BALATON Zoltan
2018-07-02  0:03         ` David Gibson
2018-06-28 22:38 ` [Qemu-devel] [PATCH v6 1/5] ppc4xx_i2c: Rewrite to model hardware more closely BALATON Zoltan
2018-07-01 23:52 ` [Qemu-devel] [PATCH v6 0/5] Misc sam460ex improvements no-reply

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