From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12E42C04EB8 for ; Mon, 10 Dec 2018 18:31:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D17DA2084C for ; Mon, 10 Dec 2018 18:31:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D17DA2084C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-pci-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728363AbeLJSbS (ORCPT ); Mon, 10 Dec 2018 13:31:18 -0500 Received: from foss.arm.com ([217.140.101.70]:60436 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726602AbeLJSbR (ORCPT ); Mon, 10 Dec 2018 13:31:17 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 38848EBD; Mon, 10 Dec 2018 10:31:17 -0800 (PST) Received: from [10.1.196.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B0B053F6A8; Mon, 10 Dec 2018 10:31:15 -0800 (PST) Subject: Re: [PATCH 0/3] PCI: designware: Fixing MSI handling flow To: Trent Piepho , "lorenzo.pieralisi@arm.com" , "gustavo.pimentel@synopsys.com" Cc: "jingoohan1@gmail.com" , "faiz_abbas@ti.com" , "linux-pci@vger.kernel.org" , "helgaas@google.com" , "vigneshr@ti.com" , "Joao.Pinto@synopsys.com" References: <20181113225734.8026-1-marc.zyngier@arm.com> <20181210161753.GA12563@e107981-ln.cambridge.arm.com> <1544465752.18519.188.camel@impinj.com> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 MIME-Version: 1.0 In-Reply-To: <1544465752.18519.188.camel@impinj.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 10/12/2018 18:15, Trent Piepho wrote: > On Mon, 2018-12-10 at 16:17 +0000, Lorenzo Pieralisi wrote: >> On Tue, Nov 13, 2018 at 10:57:31PM +0000, Marc Zyngier wrote: >>> It recently came to light that the Designware PCIe driver is rather >>> broken in the way it handles MSI[1]: >>> >>> - It masks interrupt by disabling them, meaning that MSIs generated >>> during the masked window are simply lost. Oops. >>> >>> - Acking of the currently pending MSI is done outside of the >>> interrupt >>> flow, getting moved around randomly and ultimately breaking the >>> driver. Not great. >>> >>> >> I have decided to queue this series - fixed-up as per this thread, >> available at: >> >> git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git >> test/pci-dwc-msi >> >> We allowed enough time for people to test it, we can't leave mainline >> broken for the, apparently few, people who care. >> >> I *think* that this is the Fixes: tag to be added to all patches in >> this >> series, @Gustavo please countercheck: >> >> 7c5925afbc58 ("PCI: dwc: Move MSI IRQs allocation to IRQ domains >> hierarchical API") > > That's not the correct Fixes. It should be: > > 8c934095fa2f ("PCI: dwc: Clear MSI interrupt status after it is > handled, not before") This only applies to the last one, which should carry both tags. > I had concerns about what appears to be an unnecessary extra lock taken > before handling an interrupt and enabling all MSIs even if nothing has > tried to enable them. Regarding the lock: I'm quite puzzled that you consider it "unnecessary", given that all the DWC callbacks expect such a locking. I suspect you are considering from a pure performance angle, and I'd suggest that you post numbers showing the unacceptable overhead of an otherwise uncontended lock. As for enabling all MSIs upfront, same thing. Please demonstrate how harmful it is, given that they are all masked by default, consistently with what other interrupt controllers are doing. Once you've posted some of the above, we'll queue some additional fixes on top. In the meantime, we'll fix it for everyone else. Thanks, M. -- Jazz is not dead. It just smells funny...