[U-Boot] [PATCH] mtd: nand: mxs: fix cache alignment for cache lines >32

[Stefano Babic <sbabic@denx.de>]

Hi Stefan,

On 02/08/2016 08:55, Stefan Agner wrote:
> From: Stefan Agner <stefan.agner@toradex.com>
> 
> Currently the command buffer gets allocated with a size of 32 bytes.
> This causes warning messages on systems with cache lines bigger than
> 32 bytes:
> CACHE: Misaligned operation at range [9df17a00, 9df17a20]
> 

I've never seen this on NAND....

> Define command buffer to be at least 32 bytes, but more if cache
> line is bigger.
> 
> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
> ---
> This appeared after Simon enable the message in check_cache_range
> by default...

ok, this explains why !

> 
>  drivers/mtd/nand/mxs_nand.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
> index 94fc5c1..4bf564e 100644
> --- a/drivers/mtd/nand/mxs_nand.c
> +++ b/drivers/mtd/nand/mxs_nand.c
> @@ -37,7 +37,12 @@
>  #endif
>  #define	MXS_NAND_METADATA_SIZE			10
>  #define	MXS_NAND_BITS_PER_ECC_LEVEL		13
> +
> +#if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
>  #define	MXS_NAND_COMMAND_BUFFER_SIZE		32
> +#else
> +#define	MXS_NAND_COMMAND_BUFFER_SIZE		CONFIG_SYS_CACHELINE_SIZE
> +#endif
>  
>  #define	MXS_NAND_BCH_TIMEOUT			10000
>  
> 

Reviewed-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic

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