From: "Dhanavanthri, Swathi" <swathi.dhanavanthri@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_14015227452
Date: Fri, 28 Jan 2022 08:32:14 +0000 [thread overview]
Message-ID: <bf725668ee794a309d6c6ebbd88c9388@intel.com> (raw)
In-Reply-To: <20220127194855.3963296-1-matthew.d.roper@intel.com>
Reviewed-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
-----Original Message-----
From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt Roper
Sent: Thursday, January 27, 2022 11:49 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_14015227452
Note that the bspec doesn't list the bit we're programming here (bit 11) as being present on DG2, but we've confirmed with the hardware team that this is a documentation mistake and the bit does indeed exist on all Xe_HP-based platforms.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 748b2daf043f..065dc1c2bb71 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2045,6 +2045,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) {
struct drm_i915_private *i915 = engine->i915;
+ if (IS_DG2(engine->i915)) {
+ /* Wa_14015227452:dg2 */
+ wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
+ }
+
if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2e4dd9db63fe..38c23dd36300 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8927,6 +8927,7 @@ enum {
#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
+#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
#define GEN11_DIS_PICK_2ND_EU REG_BIT(7)
#define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4)
--
2.34.1
next prev parent reply other threads:[~2022-01-28 8:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-27 19:48 [Intel-gfx] [PATCH] drm/i915/dg2: Add Wa_14015227452 Matt Roper
2022-01-27 20:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-01-27 20:43 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-28 1:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-01-28 2:22 ` Matt Roper
2022-01-28 8:32 ` Dhanavanthri, Swathi [this message]
2022-01-28 16:54 ` [Intel-gfx] [PATCH] " Matt Roper
2022-01-28 8:44 ` Tvrtko Ursulin
2022-01-28 10:03 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dg2: Add Wa_14015227452 (rev2) Patchwork
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