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Mon, 20 Sep 2021 07:47:55 -0700 (PDT) Received: from [192.168.1.11] ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id fh3sm18416588pjb.8.2021.09.20.07.47.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Sep 2021 07:47:54 -0700 (PDT) Subject: Re: [PATCH 09/30] tcg/loongarch: Implement tcg_out_mov and tcg_out_movi To: WANG Xuerui , qemu-devel@nongnu.org References: <20210920080451.408655-1-git@xen0n.name> <20210920080451.408655-10-git@xen0n.name> From: Richard Henderson Message-ID: Date: Mon, 20 Sep 2021 07:47:53 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210920080451.408655-10-git@xen0n.name> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/20/21 1:04 AM, WANG Xuerui wrote: > +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, > + tcg_target_long val) > +{ > + tcg_target_long low, upper, higher, top; > + > + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { > + val = (int32_t)val; > + } > + > + /* Single-instruction cases. */ > + low = sextreg(val, 0, 12); > + if (low == val) { > + /* val fits in simm12: addi.w rd, zero, val */ > + tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); > + return; > + } > + if (0x800 <= val && val <= 0xfff) { > + /* val fits in uimm12: ori rd, zero, val */ > + tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); > + return; > + } > + > + /* Chop upper bits into 3 immediate-field-sized segments respectively. */ > + upper = (val >> 12) & 0xfffff; > + higher = (val >> 32) & 0xfffff; > + top = val >> 52; > + > + tcg_out_opc_lu12i_w(s, rd, upper); > + if (low != 0) { > + tcg_out_opc_ori(s, rd, rd, low); > + } > + > + if (sextreg(val, 0, 32) == val) { > + /* > + * Fits in 32-bits, upper bits are already properly sign-extended by > + * lu12i.w. > + */ > + return; > + } > + tcg_out_opc_cu32i_d(s, rd, higher); > + > + if (sextreg(val, 0, 52) == val) { > + /* > + * Fits in 52-bits, upper bits are already properly sign-extended by > + * cu32i.d. > + */ > + return; > + } > + tcg_out_opc_cu52i_d(s, rd, rd, top); Looks ok. You'll want to check for small to medium pc-relative addresses. Almost every TB will load the address of TB+C (0 <= C <= 3) at the end, and the TB structure immediately precedes the code. Because of the odd values, you'll sometimes need two instructions. But that will still be less than the 3-4 for a 52/64-bit address constant. r~