From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZKXuj-0005NU-Et for qemu-devel@nongnu.org; Wed, 29 Jul 2015 16:25:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZKXud-00030a-LG for qemu-devel@nongnu.org; Wed, 29 Jul 2015 16:25:21 -0400 Received: from mail-by2on0068.outbound.protection.outlook.com ([207.46.100.68]:51904 helo=na01-by2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZKXud-00030L-7d for qemu-devel@nongnu.org; Wed, 29 Jul 2015 16:25:15 -0400 From: Alistair Francis Date: Wed, 29 Jul 2015 13:25:10 -0700 Message-ID: In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v1 15/15] xlnx-zynqmp: Connect the ZynqMP IOU SLCR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, edgar.iglesias@gmail.com, afaerber@suse.de Connect the I/O Unit System Level Control Registers device to the ZynqMP model. Unfortunately the GPIO links can not be connected yet as the SD device is not yet attached to the ZynqMP machine. Signed-off-by: Alistair Francis --- hw/arm/xlnx-zynqmp.c | 15 +++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 2 ++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 62ef4ce..deddb63 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -28,6 +28,8 @@ #define GIC_DIST_ADDR 0xf9010000 #define GIC_CPU_ADDR 0xf9020000 +#define IOU_SLCR_ADDR 0xFF180000 + static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, }; @@ -90,6 +92,10 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART); qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); } + + object_initialize(&s->iou_slcr, sizeof(s->iou_slcr), + TYPE_XLNX_ZYNQMP_IOU_SLCR); + qdev_set_parent_bus(DEVICE(&s->iou_slcr), sysbus_get_default()); } static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -235,6 +241,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, gic_spi[uart_intr[i]]); } + + object_property_set_bool(OBJECT(&s->iou_slcr), true, "realized", &err); + if (err) { + error_propagate((errp), (err)); + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->iou_slcr), 0, + TYPE_XLNX_ZYNQMP_IOU_SLCR); } static Property xlnx_zynqmp_props[] = { diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c379632..96b1e97 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -22,6 +22,7 @@ #include "hw/intc/arm_gic.h" #include "hw/net/cadence_gem.h" #include "hw/char/cadence_uart.h" +#include "hw/misc/xlnx-zynqmp-iou-slcr.h" #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ @@ -54,6 +55,7 @@ typedef struct XlnxZynqMPState { MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; + XlnxZynqMPIOUSLCR iou_slcr; char *boot_cpu; ARMCPU *boot_cpu_ptr; -- 1.7.1