Commen=
t # 5
on bug 10251=
1
from Rob MacKinnon
Comments inline...
(In reply to Alex Deucher from comm=
ent #2)
> (In reply to Rob MacKinnon from comment #0)
> > * Actual Result:
> > - DPMS change level changes as expected.
> > - Dmesg:
> > [ 3302.814889] [drm:btc_dpm_set_power_state [radeon]] *ERROR*
> > rv770_restrict_performance_levels_before_switch failed
> > [ 3316.661933] [drm:btc_dpm_set_power_state [radeon]] *ERROR*
> > rv770_restrict_performance_levels_before_switch failed
> >=20
> > * Expected result:
> > - DPMS change level changes as expected.
> > - No error messages in dmesg.
>=20
> Are you actually experiencing any problems? I think the error message=
may
> be harmless can could probably be removed.
The annoyance of the message is totally trivial, but I believe there is an
issue with the initial setting of the DPMS profile. Which I'll mention in t=
he
next comment.
> >=20
> > * Additional Info:
> > Also, not sure if this is related or not, when switching from &qu=
ot;battery" to
> > "performance" there sometimes appears to be an initial =
clocking issue (which
> > I believe is related to #93753). Switching back and forth a few t=
imes seems
> > to clean it. Unsure the cause. Another note, upon further inspe=
ction of my
>=20
> There is no real balanced state. It's either battery or performance
> depending on whether the chip is on ac or dc power. The only real sta=
tes
> you can switch between are performance and battery. I need to see the
> output of our dmesg with radeon.dpm=3D1 to see what states your vbios =
provides.
I believe you when you say that the `balanced` state is non-existent. A ch=
eck
after cold starting shows that `balanced` is the first profile being set:
# cat /sys/class/drm/card0/device/power_dpm_state
balanced
So I'm not sure where this profile is being set from.
>=20
> > DPMS settings, I noticed the drastic differences between "ba=
lanced" and
> > "battery" `sclk`s. My understand (which could be faulty=
) is that `sclk`
> > drives the clocking for single displays, while `mclk` for multipl=
e. My
>=20
> sclk is the 3D engine clock. mclk is the memory clock. mclk switchin=
g is
> disabled when multiple displays are active since the switch has to hap=
pen
> during the display's vblank period otherwise you'd see display glitche=
s.=20
> With multiple displays, the vblank periods are not likely to align so =
mclk
> switching is disabled.
Thank you very much for clarifying the function of `sclk` vs `mclk`. That's
great info, I wish I'd been able to find it elsewhere. My google-fu was the
source of my original understanding (which as it turns out was completely
wrong).
Regardless, somewhere the `balanced` profile is getting pulled from with
greatly under valued 3D clocking value. Is there a setting somewhere that I
can trace down where this invalid profile is being generated or referenced?=