(In reply to Rob MacKinnon from comment #0)
> * Actual Result:
> - DPMS change level changes as expected.
> - Dmesg:
> [ 3302.814889] [drm:btc_dpm_set_power_state [radeon]] *ERROR*
> rv770_restrict_performance_levels_before_switch failed
> [ 3316.661933] [drm:btc_dpm_set_power_state [radeon]] *ERROR*
> rv770_restrict_performance_levels_before_switch failed
>=20
> * Expected result:
> - DPMS change level changes as expected.
> - No error messages in dmesg.

Are you actually experiencing any problems?  I think the error message may =
be
harmless can could probably be removed.

>=20
> * Additional Info:
> Also, not sure if this is related or not, when switching from "ba=
ttery" to
> "performance" there sometimes appears to be an initial clock=
ing issue (which
> I believe is related to #93753). Switching back and forth a few times =
seems
> to clean it.  Unsure the cause.  Another note, upon further inspection=
 of my

There is no real balanced state.  It's either battery or performance depend=
ing
on whether the chip is on ac or dc power.  The only real states you can swi=
tch
between are performance and battery.  I need to see the output of our dmesg
with radeon.dpm=3D1 to see what states your vbios provides.

> DPMS settings, I noticed the drastic differences=
 between "balanced" and
> "battery" `sclk`s. My understand (which could be faulty) is =
that `sclk`
> drives the clocking for single displays, while `mclk` for multiple. My=

sclk is the 3D engine clock.  mclk is the memory clock.  mclk switching is
disabled when multiple displays are active since the switch has to happen
during the display's vblank period otherwise you'd see display glitches.  W=
ith
multiple displays, the vblank periods are not likely to align so mclk switc=
hing
is disabled.