[Bug 107296] WARNING: CPU: 0 PID: 370 at drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dcn_calcs.c:1355 dcn_bw_update_from_pplib+0x16b/0x280 [amdgpu]

[bugzilla-daemon@freedesktop.org]

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https://bugs.freedesktop.org/show_bug.cgi?id=107296

Janpieter Sollie <janpieter.sollie@dommel.be> changed:

           What    |Removed                     |Added
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 Attachment #144689|0                           |1
        is obsolete|                            |

--- Comment #21 from Janpieter Sollie <janpieter.sollie@dommel.be> ---
Created attachment 145764
  --> https://bugs.freedesktop.org/attachment.cgi?id=145764&action=edit
dmesg of PPLIB error

still present on linux 5.3, with the following exceptions:
- the values in mV seem to be initialized,
- DRM does not complain about 'Cannot find any crtc or sizes' after GPU adding
- DRM: construct error is gone

So it's going the good way, I guess ...
I investigated the source around dcn_bw_update_from_pplib

And I saw the following code in gpu/drm/amd/display/dc/calcs/dcn_calcs.c

========================================
        bool res;

        /* TODO: This is not the proper way to obtain
fabric_and_dram_bandwidth, should be min(fclk, memclk) */
        res = dm_pp_get_clock_levels_by_type_with_voltage(
                        ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);

        kernel_fpu_begin();

        if (res)
                res = verify_clock_values(&fclks);

        if (res) {
//unimportant, left out
        } else
                BREAK_TO_DEBUGGER();
=============================================

which probably explains what happens: fclks gets a number of clock values from
dm_pp_get_clock_levels_by_type_with_voltage, setting res to true.
It tries to validate the clock values then, which fails because of the invalid
numbers
After that, it breaks to debugger.

Is it possible the vega11 needs more time to initialize its clock limits?

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