I think you need to be a vesa member to download the DP specs.  There may be
some older copies floating around on the internet.  They are also available to
Xorg members if you wanted to become an Xorg member.

As to the problem, the link training sequence has defined delays for various
parts of the training sequence.  I would suggest tweaking the existing delays
rather than adding new ones.  E.g., the udelay(400); in
radeon_dp_link_train_cr() and radeon_dp_link_train_finish() and the delays in
drm_dp_link_train_clock_recovery_delay() and
drm_dp_link_train_channel_eq_delay().  Or possibly passing different delays to
radeon_dp_aux_native_read() or radeon_dp_aux_native_write().