[Bug 75241] radeon_compute_pll_avivo broken in 3.15-rc3

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https://bugzilla.kernel.org/show_bug.cgi?id=75241

--- Comment #5 from Clemens Ladisch <clemens@ladisch.de> ---
It's an Eizo S2100, but this should not matter because the clocks seen by the
monitor are always about the same (162MHz/75kHz/60Hz).  If some were out of
range, the monitor would show an error message, but with the PLL problem, the
monitor does not appear to detect even an out-of-range signal.   I'd guess the
PLL itself cannot handle the parameters.

The largest working ref_div_max limit is 131.

with 131:  162000 - 161990, pll dividers - fb: 1425.4 ref: 21, post 6

with 132:  162000 - 162000, pll dividers - fb: 1493.3 ref: 22, post 6

avivo_reduce_ratio does not change these values.

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