From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 82050] R9270X pyrit benchmark perf regressions with latest kernel/llvm Date: Tue, 05 Aug 2014 23:23:26 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2002969644==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id AD5876E0EA for ; Tue, 5 Aug 2014 16:23:26 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============2002969644== Content-Type: multipart/alternative; boundary="1407281006.cca1AE0E0.27514"; charset="us-ascii" --1407281006.cca1AE0E0.27514 Date: Tue, 5 Aug 2014 23:23:26 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable https://bugs.freedesktop.org/show_bug.cgi?id=3D82050 --- Comment #8 from Andy Furniss --- kernel - fb240a2534802a86742db51b7334138675bc435e is the first bad commit commit fb240a2534802a86742db51b7334138675bc435e Author: Michel D=C3=A4nzer Date: Thu Jul 31 18:43:49 2014 +0900 drm/radeon: Always flush the HDP cache before submitting a CS to the GPU This ensures the GPU sees all previous CPU writes to VRAM, which makes = it safe: * For userspace to stream data from CPU to GPU via VRAM instead of GTT * For IBs to be stored in VRAM instead of GTT * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush is performed via MMIO Signed-off-by: Michel D=C3=A4nzer Signed-off-by: Alex Deucher --=20 You are receiving this mail because: You are the assignee for the bug. --1407281006.cca1AE0E0.27514 Date: Tue, 5 Aug 2014 23:23:26 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Comment= # 8 on bug 82050<= /a> from Andy Furniss 
kernel -

fb240a2534802a86742db51b7334138675bc435e is the first bad commit
commit fb240a2534802a86742db51b7334138675bc435e
Author: Michel D=C3=A4nzer <michel.daenzer@amd.com>
Date:   Thu Jul 31 18:43:49 2014 +0900

    drm/radeon: Always flush the HDP cache before submitting a CS to the GPU

    This ensures the GPU sees all previous CPU writes to VRAM, which makes =
it
    safe:

    * For userspace to stream data from CPU to GPU via VRAM instead of GTT
    * For IBs to be stored in VRAM instead of GTT
    * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush
      is performed via MMIO

    Signed-off-by: Michel D=C3=A4nzer <michel.daenzer@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

You are receiving this mail because: =20=20=20=20=20=20
  • You are the assignee for the bug.
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