From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 91749] Tonga IH ring misaligned Date: Tue, 25 Aug 2015 01:18:08 +0000 Message-ID: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1536199056==" Return-path: Received: from culpepper.freedesktop.org (unknown [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id C4B256E003 for ; Mon, 24 Aug 2015 18:18:08 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1536199056== Content-Type: multipart/alternative; boundary="1440465488.1E10a30.4858"; charset="UTF-8" --1440465488.1E10a30.4858 Date: Tue, 25 Aug 2015 01:18:08 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" https://bugs.freedesktop.org/show_bug.cgi?id=91749 Bug ID: 91749 Summary: Tonga IH ring misaligned Product: DRI Version: DRI git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel@lists.freedesktop.org Reporter: jay@jcornwall.me >>From amdgpu_ih.c: adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL); if (adev->irq.ih.ring == NULL) return -ENOMEM; adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev, (void *)adev->irq.ih.ring, adev->irq.ih.ring_size, PCI_DMA_BIDIRECTIONAL); The Tonga IH_RB_BASE register requires 256B alignment. kzalloc does not guarantee this, e.g.: adev->irq.ih.ring: 0xFFFF880835B22148 adev->irq.ih.rb_dma_addr: 0x835B22148 IH_RB_BASE: 0835b221 This causes amdgpu_ih_decode_iv to read ahead of the last written IV, missing it, when this misalignment occurs. -- You are receiving this mail because: You are the assignee for the bug. --1440465488.1E10a30.4858 Date: Tue, 25 Aug 2015 01:18:08 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8"
Bug ID 91749
Summary Tonga IH ring misaligned
Product DRI
Version DRI git
Hardware Other
OS All
Status NEW
Severity normal
Priority medium
Component DRM/AMDgpu
Assignee dri-devel@lists.freedesktop.org
Reporter jay@jcornwall.me 

From amdgpu_ih.c:

      adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL);
      if (adev->irq.ih.ring == NULL)
        return -ENOMEM;
      adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev,
                  (void *)adev->irq.ih.ring,
                  adev->irq.ih.ring_size,
                  PCI_DMA_BIDIRECTIONAL);

The Tonga IH_RB_BASE register requires 256B alignment. kzalloc does not
guarantee this, e.g.:

adev->irq.ih.ring: 0xFFFF880835B22148
adev->irq.ih.rb_dma_addr: 0x835B22148
IH_RB_BASE: 0835b221

This causes amdgpu_ih_decode_iv to read ahead of the last written IV, missing
it, when this misalignment occurs.

You are receiving this mail because:
  • You are the assignee for the bug.
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