From mboxrd@z Thu Jan 1 00:00:00 1970
From: bugzilla-daemon@freedesktop.org
Subject: [Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0
clock gate feature" sets MCLK on highest state
Date: Tue, 22 Nov 2016 21:36:00 +0000
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Date: Tue, 22 Nov 2016 21:36:00 +0000
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--- Comment #7 from Arek Ru=C5=9Bniak ---
Alex I use something like that:
watch -n 1 -c "cat /sys/kernel/debug/dri/0/amdgpu_pm_info"
combined with=20
vblank_mode=3D0 glxgears
it should set mclk on fire IIRC, but it was still 300MHz, bisecting gives m=
e:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=3Ddrm-next-4.10-wip&id=
=3Dddfe1db18752b08d88d81cb7b661e1f982fc5d04
but when I've tested (in the bisecting proces) commit [1] I saw that mclk i=
set
always on 2000MHz... and this is first commit (I checked +/- 1) when is set=
on
HIGH no matter what.
So yes, this are two issues in one I believe because revert
1b7eab1f8346ab3b8e4fc54882306340a84497a8 fixes them all.
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