Can you clarify the situation a bit?  I take it there are two issues?

With commit:
drm/amdgpu: refine uvd 6.0 clock gate feature
does the mclk always stay high?  With this reverted does it go up and down on
demand?  Is this just an issue with two monitors attached?  Do you also see it
with only one monitor attached?

With commit:
drm/amdgpu:impl vgt_flush for VI(V5)
is the mclk always stuck in low?  Do you not see to adjusting on the fly based
on load?

Please use /sys/kernel/debug/dri/64/amdgpu_pm_info to verify the clocks at
runtime.