From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state Date: Tue, 22 Nov 2016 20:31:50 +0000 Message-ID: References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0868463935==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id 8484B6E2C3 for ; Tue, 22 Nov 2016 20:31:50 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0868463935== Content-Type: multipart/alternative; boundary="14798467100.fdb2534C.10424"; charset="UTF-8" --14798467100.fdb2534C.10424 Date: Tue, 22 Nov 2016 20:31:50 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D98821 --- Comment #1 from Alex Deucher --- Can you clarify the situation a bit? I take it there are two issues? With commit: drm/amdgpu: refine uvd 6.0 clock gate feature does the mclk always stay high? With this reverted does it go up and down = on demand? Is this just an issue with two monitors attached? Do you also see= it with only one monitor attached? With commit: drm/amdgpu:impl vgt_flush for VI(V5) is the mclk always stuck in low? Do you not see to adjusting on the fly ba= sed on load? Please use /sys/kernel/debug/dri/64/amdgpu_pm_info to verify the clocks at runtime. --=20 You are receiving this mail because: You are the assignee for the bug.= --14798467100.fdb2534C.10424 Date: Tue, 22 Nov 2016 20:31:50 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated

Comment= # 1 on bug 98821<= /a> from Alex Deucher 
Can you clarify the situation a bit?  I take it there are two =
issues?

With commit:
drm/amdgpu: refine uvd 6.0 clock gate feature
does the mclk always stay high?  With this reverted does it go up and down =
on
demand?  Is this just an issue with two monitors attached?  Do you also see=
 it
with only one monitor attached?

With commit:
drm/amdgpu:impl vgt_flush for VI(V5)
is the mclk always stuck in low?  Do you not see to adjusting on the fly ba=
sed
on load?

Please use /sys/kernel/debug/dri/64/amdgpu_pm_info to verify the clocks at
runtime.

You are receiving this mail because:
  • You are the assignee for the bug.
= --14798467100.fdb2534C.10424-- --===============0868463935== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============0868463935==--