From mboxrd@z Thu Jan 1 00:00:00 1970 From: bugzilla-daemon@freedesktop.org Subject: [Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state Date: Tue, 22 Nov 2016 20:11:27 +0000 Message-ID: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0990067448==" Return-path: Received: from culpepper.freedesktop.org (culpepper.freedesktop.org [131.252.210.165]) by gabe.freedesktop.org (Postfix) with ESMTP id E8F856E67B for ; Tue, 22 Nov 2016 20:11:26 +0000 (UTC) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============0990067448== Content-Type: multipart/alternative; boundary="14798454860.3B32A8fa.9363"; charset="UTF-8" --14798454860.3B32A8fa.9363 Date: Tue, 22 Nov 2016 20:11:26 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated https://bugs.freedesktop.org/show_bug.cgi?id=3D98821 Bug ID: 98821 Summary: [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state Product: DRI Version: DRI git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel@lists.freedesktop.org Reporter: arek.rusi@gmail.com Hi, before this commit MCLK works ok, reverting did the job.=C2=A0=20 [1] drm/amdgpu: refine uvd 6.0 clock gate feature https://cgit.freedesktop.org/~agd5f/linux/commit/?h=3Ddrm-next-4.10-wip&id= =3D1b7eab1f8346ab3b8e4fc54882306340a84497a8 There is two stages for this issue: [1] MCLK is HIGH (maybe more power consumption) [2] MCLK is LOW - performance hit. [1]for idle (two displays but only one is active) cat /sys/class/drm/card0/device/pp_dpm_sclk=20 0: 300Mhz * 1: 466Mhz=20 2: 751Mhz=20 3: 1019Mhz=20 4: 1074Mhz=20 5: 1126Mhz=20 6: 1169Mhz=20 7: 1260Mhz cat /sys/class/drm/card0/device/pp_dpm_mclk=20 0: 300Mhz=20 1: 2000Mhz * [2]drm/amdgpu:impl vgt_flush for VI(V5) https://cgit.freedesktop.org/~agd5f/linux/commit/?h=3Ddrm-next-4.10-wip&id= =3Dddfe1db18752b08d88d81cb7b661e1f982fc5d04 MCLK is set to LOWEST state (300MHz) and nothing can change that until reve= rt [1]. --=20 You are receiving this mail because: You are the assignee for the bug.= --14798454860.3B32A8fa.9363 Date: Tue, 22 Nov 2016 20:11:26 +0000 MIME-Version: 1.0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://bugs.freedesktop.org/ Auto-Submitted: auto-generated
Bug ID 98821
Summary [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 = clock gate feature" sets MCLK on highest state
Product DRI
Version DRI git
Hardware Other
OS All
Status NEW
Severity normal
Priority medium
Component DRM/AMDgpu
Assignee dri-devel@lists.freedesktop.org
Reporter arek.rusi@gmail.com 

Hi, before this commit MCLK works ok, reverting did the job.=
=C2=A0=20
[1] drm/amdgpu: refine uvd 6.0 clock gate feature
https://cgit.fre=
edesktop.org/~agd5f/linux/commit/?h=3Ddrm-next-4.10-wip&id=3D1b7eab1f83=
46ab3b8e4fc54882306340a84497a8

There is two stages for this issue:
[1] MCLK is HIGH (maybe more power consumption)
[2] MCLK is LOW - performance hit.

[1]for idle (two displays but only one is active)
cat /sys/class/drm/card0/device/pp_dpm_sclk=20
0: 300Mhz *
1: 466Mhz=20
2: 751Mhz=20
3: 1019Mhz=20
4: 1074Mhz=20
5: 1126Mhz=20
6: 1169Mhz=20
7: 1260Mhz
cat /sys/class/drm/card0/device/pp_dpm_mclk=20
0: 300Mhz=20
1: 2000Mhz *

[2]drm/amdgpu:impl vgt_flush for VI(V5)
https://cgit.fre=
edesktop.org/~agd5f/linux/commit/?h=3Ddrm-next-4.10-wip&id=3Dddfe1db187=
52b08d88d81cb7b661e1f982fc5d04
MCLK is set to LOWEST state (300MHz) and nothing can change that until reve=
rt
[1].

You are receiving this mail because:
  • You are the assignee for the bug.
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