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Wed, 9 Dec 2020 01:22:32 +0000 Message-ID: Subject: Re: [PATCH 2/4] phy: Add LVDS configuration options From: Liu Ying To: Laurent Pinchart Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, a.hajda@samsung.com, narmstrong@baylibre.com, jonas@kwiboo.se, jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, agx@sigxcpu.org, robert.chiras@nxp.com, martin.kepplinger@puri.sm Date: Wed, 09 Dec 2020 09:20:40 +0800 In-Reply-To: References: <1607067224-15616-1-git-send-email-victor.liu@nxp.com> <1607067224-15616-3-git-send-email-victor.liu@nxp.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.4-0ubuntu1 Content-Transfer-Encoding: 7bit X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR04CA0181.apcprd04.prod.outlook.com (2603:1096:4:14::19) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from blueberry.ap.freescale.net (119.31.174.66) by SG2PR04CA0181.apcprd04.prod.outlook.com (2603:1096:4:14::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.12 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?B?am1WWHpLR0kwQzNqb3NFVkw5d3Z6Rnd2b2tUVVpjSXE4d01yQXZxM0FqNEdO?= =?utf-8?B?TWYrbjg5T1dUSjFyUG8yNHVIRml1TFErbEtOUDE1bFVtUUtWWlBZVkpKQTNR?= =?utf-8?B?VGllZm1DTHZTa1JHTFZCRnV0cjZGNGpWblkvd3lUbnV1N3dpVmIyb1pGY01j?= =?utf-8?B?Qk5EeUg2RHo5UlJ4L0xxaXJlY2ZCbVIxZDArbHlqVlB4L3lFeTYyTWR4Q3Bu?= =?utf-8?B?cm9LQlU3R0pleW5GTE1Fc05tQjlYZ0U0TmFEWXpjZFJndmd0V1lCVExzK2RI?= =?utf-8?B?c0VKeEt1TnVURjFhVWY3a1dtN3hDbmUrQm1JK0VJN2Y5WSt5OENSVFJ4alVm?= =?utf-8?B?NmxpQkpFTnpBMk5lclVMajdwckVhYUJaMU1LRzE0UGk5NUNSdENrNGRxU2tq?= =?utf-8?B?elNkVUxhRWdlOG9SZ3BPVFhUYVlsVWZWZHkvOWNvellWOUtuQUQwREJkMHZ2?= =?utf-8?B?TmJCUmdGa1ZVTTRFQjBmR016S0dtNWV4alhoY0RzRmZZL1pIWnc4ZnYzRmVO?= =?utf-8?B?RGVWM0RYbHorblRYeEw3akZ6cjJkUU9pSUI3RXVxaTdBVEVIeXhqbEdyNUxK?= =?utf-8?B?a2kxMEFGTVhRWXEvTzNVam1pT0F6eGxTcmtQNUhDY29qVkkvdElHSi9oM0do?= =?utf-8?B?b3lKZFZ4V283OWptdW1ScG0wNU1RZkdnQ3l3bmkyVDBrSHpwZ3hZbHFRTmpX?= =?utf-8?B?YXdyWWFvZXViRm11cWRqSjhDemluM0xVbmF3VmZmUnh1eXVBUWx0UjRLcHRE?= =?utf-8?B?c1U3NHZkZVRBK3YxMnNOSG8xUWxHZ3Jldm05a2tFQ1didmovOW9hdUFrTis0?= =?utf-8?B?NU02SzZNMUxqdHRlL1E3K2hoSFZJQ3Fjd2g5N1BiK0lYMVF1WlVjQ1h1dUlC?= =?utf-8?B?ajI4UldTTVliemRQV3ZqWExVOXNHKytCdDIyZFdjaG5hSklRTk90NWdTNWdR?= =?utf-8?B?SlBia09GeEN2SHFYbWwvV0VWdlBDZytZTWV3NnpEMjJVajZNQXFuSHo0NXNL?= =?utf-8?B?VXU3bldUT3RuMUhHa1E2c1dkclNsbjNMc29YNURTclljdGRnMVpYdkNlUkFv?= =?utf-8?B?S280UFkwWFVoY0RnV1luUmoxdWlBb2JseDJmMzBWcE91RlpDNU0vUEswdHlw?= =?utf-8?B?WDhJQjBPNkphNE9TSkRqWGlQa3d2MUc1ZTExMDA4NWJxNTA0VUs2YmcwUXRU?= =?utf-8?B?Qkw4bElsV3VkZ2RzNHBjeXZXS1dqaWQrTlZTUVpxYWNldVdhdklNMlFCY0lo?= =?utf-8?B?d1JzMVBrMnI4NHJRVUlKMWJ0WFdNanJqNlRCWUdOS2hHSE5SN1EybEl5Qm5T?= =?utf-8?Q?sO4eMpIWmj9OI9HN59qRUaKD+vle/AU17N?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2020 01:22:32.1346 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-Network-Message-Id: e0afbfd6-c7c6-49f7-920d-08d89be0e6fa X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qg5UQAWdWcaiWHEi8n6Uvy8JSXqPkiqjdHNGoi4PkWFRmKC6ClnOe2h1ura1RHC7EcxNtPL/WXYk5IftzhYplA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3423 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Laurent, On Tue, 2020-12-08 at 14:38 +0200, Laurent Pinchart wrote: > Hi Liu, > > Thank you for the patch. > > On Fri, Dec 04, 2020 at 03:33:42PM +0800, Liu Ying wrote: > > This patch allows LVDS PHYs to be configured through > > the generic functions and through a custom structure > > added to the generic union. > > > > The parameters added here are based on common LVDS PHY > > implementation practices. The set of parameters > > should cover all potential users. > > > > Cc: Kishon Vijay Abraham I > > Cc: Vinod Koul > > Cc: NXP Linux Team > > Signed-off-by: Liu Ying > > --- > > include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++ > > include/linux/phy/phy.h | 4 ++++ > > 2 files changed, 52 insertions(+) > > create mode 100644 include/linux/phy/phy-lvds.h > > > > diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h > > new file mode 100644 > > index 00000000..1b5b9d6 > > --- /dev/null > > +++ b/include/linux/phy/phy-lvds.h > > @@ -0,0 +1,48 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright 2020 NXP > > + */ > > + > > +#ifndef __PHY_LVDS_H_ > > +#define __PHY_LVDS_H_ > > + > > +/** > > + * struct phy_configure_opts_lvds - LVDS configuration set > > + * > > + * This structure is used to represent the configuration state of a > > + * LVDS phy. > > + */ > > +struct phy_configure_opts_lvds { > > + /** > > + * @bits_per_lane_and_dclk_cycle: > > + * > > + * Number of bits per data lane and differential clock cycle. > > + */ > > + unsigned int bits_per_lane_and_dclk_cycle; > > I see in patch 4/4 that you only support 7, can the value be any > different ? Patch 4/4 is for the Mixel combo PHY embedded in i.MX8qxp SoC. This PHY can only do 7. i.MX8qm SoC embeds another type of Mixel LVDS PHY which can do either 7 or 10(configurable with a register bit called 'NB'). A PHY driver for it is yet to be upstreamed. Regards, Liu Ying > > > + > > + /** > > + * @differential_clk_rate: > > + * > > + * Clock rate, in Hertz, of the LVDS differential clock. > > + */ > > + unsigned long differential_clk_rate; > > + > > + /** > > + * @lanes: > > + * > > + * Number of active, consecutive, data lanes, starting from > > + * lane 0, used for the transmissions. > > + */ > > + unsigned int lanes; > > + > > + /** > > + * @is_slave: > > + * > > + * Boolean, true if the phy is a slave which works together > > + * with a master phy to support dual link transmission, > > + * otherwise a regular phy or a master phy. > > + */ > > + bool is_slave; > > +}; > > + > > +#endif /* __PHY_LVDS_H_ */ > > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h > > index e435bdb..d450b44 100644 > > --- a/include/linux/phy/phy.h > > +++ b/include/linux/phy/phy.h > > @@ -17,6 +17,7 @@ > > #include > > > > #include > > +#include > > #include > > > > struct phy; > > @@ -51,10 +52,13 @@ enum phy_mode { > > * the MIPI_DPHY phy mode. > > * @dp: Configuration set applicable for phys supporting > > * the DisplayPort protocol. > > + * @lvds: Configuration set applicable for phys supporting > > + * the LVDS phy mode. > > */ > > union phy_configure_opts { > > struct phy_configure_opts_mipi_dphy mipi_dphy; > > struct phy_configure_opts_dp dp; > > + struct phy_configure_opts_lvds lvds; > > }; > > > > /** From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A340C433FE for ; Wed, 9 Dec 2020 01:24:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C0ABF239E5 for ; Wed, 9 Dec 2020 01:24:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C0ABF239E5 Authentication-Results: mail.kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Laurent, On Tue, 2020-12-08 at 14:38 +0200, Laurent Pinchart wrote: > Hi Liu, > > Thank you for the patch. > > On Fri, Dec 04, 2020 at 03:33:42PM +0800, Liu Ying wrote: > > This patch allows LVDS PHYs to be configured through > > the generic functions and through a custom structure > > added to the generic union. > > > > The parameters added here are based on common LVDS PHY > > implementation practices. The set of parameters > > should cover all potential users. > > > > Cc: Kishon Vijay Abraham I > > Cc: Vinod Koul > > Cc: NXP Linux Team > > Signed-off-by: Liu Ying > > --- > > include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++ > > include/linux/phy/phy.h | 4 ++++ > > 2 files changed, 52 insertions(+) > > create mode 100644 include/linux/phy/phy-lvds.h > > > > diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h > > new file mode 100644 > > index 00000000..1b5b9d6 > > --- /dev/null > > +++ b/include/linux/phy/phy-lvds.h > > @@ -0,0 +1,48 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright 2020 NXP > > + */ > > + > > +#ifndef __PHY_LVDS_H_ > > +#define __PHY_LVDS_H_ > > + > > +/** > > + * struct phy_configure_opts_lvds - LVDS configuration set > > + * > > + * This structure is used to represent the configuration state of a > > + * LVDS phy. > > + */ > > +struct phy_configure_opts_lvds { > > + /** > > + * @bits_per_lane_and_dclk_cycle: > > + * > > + * Number of bits per data lane and differential clock cycle. > > + */ > > + unsigned int bits_per_lane_and_dclk_cycle; > > I see in patch 4/4 that you only support 7, can the value be any > different ? Patch 4/4 is for the Mixel combo PHY embedded in i.MX8qxp SoC. This PHY can only do 7. i.MX8qm SoC embeds another type of Mixel LVDS PHY which can do either 7 or 10(configurable with a register bit called 'NB'). A PHY driver for it is yet to be upstreamed. Regards, Liu Ying > > > + > > + /** > > + * @differential_clk_rate: > > + * > > + * Clock rate, in Hertz, of the LVDS differential clock. > > + */ > > + unsigned long differential_clk_rate; > > + > > + /** > > + * @lanes: > > + * > > + * Number of active, consecutive, data lanes, starting from > > + * lane 0, used for the transmissions. > > + */ > > + unsigned int lanes; > > + > > + /** > > + * @is_slave: > > + * > > + * Boolean, true if the phy is a slave which works together > > + * with a master phy to support dual link transmission, > > + * otherwise a regular phy or a master phy. > > + */ > > + bool is_slave; > > +}; > > + > > +#endif /* __PHY_LVDS_H_ */ > > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h > > index e435bdb..d450b44 100644 > > --- a/include/linux/phy/phy.h > > +++ b/include/linux/phy/phy.h > > @@ -17,6 +17,7 @@ > > #include > > > > #include > > +#include > > #include > > > > struct phy; > > @@ -51,10 +52,13 @@ enum phy_mode { > > * the MIPI_DPHY phy mode. > > * @dp: Configuration set applicable for phys supporting > > * the DisplayPort protocol. > > + * @lvds: Configuration set applicable for phys supporting > > + * the LVDS phy mode. > > */ > > union phy_configure_opts { > > struct phy_configure_opts_mipi_dphy mipi_dphy; > > struct phy_configure_opts_dp dp; > > + struct phy_configure_opts_lvds lvds; > > }; > > > > /** _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ECA1C4167B for ; Wed, 9 Dec 2020 08:32:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 02D4723B97 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Laurent, On Tue, 2020-12-08 at 14:38 +0200, Laurent Pinchart wrote: > Hi Liu, > > Thank you for the patch. > > On Fri, Dec 04, 2020 at 03:33:42PM +0800, Liu Ying wrote: > > This patch allows LVDS PHYs to be configured through > > the generic functions and through a custom structure > > added to the generic union. > > > > The parameters added here are based on common LVDS PHY > > implementation practices. The set of parameters > > should cover all potential users. > > > > Cc: Kishon Vijay Abraham I > > Cc: Vinod Koul > > Cc: NXP Linux Team > > Signed-off-by: Liu Ying > > --- > > include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++ > > include/linux/phy/phy.h | 4 ++++ > > 2 files changed, 52 insertions(+) > > create mode 100644 include/linux/phy/phy-lvds.h > > > > diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h > > new file mode 100644 > > index 00000000..1b5b9d6 > > --- /dev/null > > +++ b/include/linux/phy/phy-lvds.h > > @@ -0,0 +1,48 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright 2020 NXP > > + */ > > + > > +#ifndef __PHY_LVDS_H_ > > +#define __PHY_LVDS_H_ > > + > > +/** > > + * struct phy_configure_opts_lvds - LVDS configuration set > > + * > > + * This structure is used to represent the configuration state of a > > + * LVDS phy. > > + */ > > +struct phy_configure_opts_lvds { > > + /** > > + * @bits_per_lane_and_dclk_cycle: > > + * > > + * Number of bits per data lane and differential clock cycle. > > + */ > > + unsigned int bits_per_lane_and_dclk_cycle; > > I see in patch 4/4 that you only support 7, can the value be any > different ? Patch 4/4 is for the Mixel combo PHY embedded in i.MX8qxp SoC. This PHY can only do 7. i.MX8qm SoC embeds another type of Mixel LVDS PHY which can do either 7 or 10(configurable with a register bit called 'NB'). A PHY driver for it is yet to be upstreamed. Regards, Liu Ying > > > + > > + /** > > + * @differential_clk_rate: > > + * > > + * Clock rate, in Hertz, of the LVDS differential clock. > > + */ > > + unsigned long differential_clk_rate; > > + > > + /** > > + * @lanes: > > + * > > + * Number of active, consecutive, data lanes, starting from > > + * lane 0, used for the transmissions. > > + */ > > + unsigned int lanes; > > + > > + /** > > + * @is_slave: > > + * > > + * Boolean, true if the phy is a slave which works together > > + * with a master phy to support dual link transmission, > > + * otherwise a regular phy or a master phy. > > + */ > > + bool is_slave; > > +}; > > + > > +#endif /* __PHY_LVDS_H_ */ > > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h > > index e435bdb..d450b44 100644 > > --- a/include/linux/phy/phy.h > > +++ b/include/linux/phy/phy.h > > @@ -17,6 +17,7 @@ > > #include > > > > #include > > +#include > > #include > > > > struct phy; > > @@ -51,10 +52,13 @@ enum phy_mode { > > * the MIPI_DPHY phy mode. > > * @dp: Configuration set applicable for phys supporting > > * the DisplayPort protocol. > > + * @lvds: Configuration set applicable for phys supporting > > + * the LVDS phy mode. > > */ > > union phy_configure_opts { > > struct phy_configure_opts_mipi_dphy mipi_dphy; > > struct phy_configure_opts_dp dp; > > + struct phy_configure_opts_lvds lvds; > > }; > > > > /** _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel