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From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return
Date: Thu, 5 Oct 2017 12:04:43 -0400	[thread overview]
Message-ID: <c0b514b4-6474-87ed-6fa0-c109761d243c@linaro.org> (raw)
In-Reply-To: <1506092407-26985-3-git-send-email-peter.maydell@linaro.org>

On 09/22/2017 10:59 AM, Peter Maydell wrote:
> Currently our M profile exception return code switches to the
> target stack pointer relatively early in the process, before
> it tries to pop the exception frame off the stack. This is
> awkward for v8M for two reasons:
>  * in v8M the process vs main stack pointer is not selected
>    purely by the value of CONTROL.SPSEL, so updating SPSEL
>    and relying on that to switch to the right stack pointer
>    won't work
>  * the stack we should be reading the stack frame from and
>    the stack we will eventually switch to might not be the
>    same if the guest is doing strange things
> 
> Change our exception return code to use a 'frame pointer'
> to read the exception frame rather than assuming that we
> can switch the live stack pointer this early.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/helper.c | 127 +++++++++++++++++++++++++++++++++++++++-------------
>  1 file changed, 95 insertions(+), 32 deletions(-)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 8be78ea..f13b99d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6040,16 +6040,6 @@ static void v7m_push(CPUARMState *env, uint32_t val)
>      stl_phys(cs->as, env->regs[13], val);
>  }
>  
> -static uint32_t v7m_pop(CPUARMState *env)
> -{
> -    CPUState *cs = CPU(arm_env_get_cpu(env));
> -    uint32_t val;
> -
> -    val = ldl_phys(cs->as, env->regs[13]);
> -    env->regs[13] += 4;
> -    return val;
> -}
> -
>  /* Return true if we're using the process stack pointer (not the MSP) */
>  static bool v7m_using_psp(CPUARMState *env)
>  {
> @@ -6141,6 +6131,40 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
>      env->regs[15] = dest & ~1;
>  }
>  
> +static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
> +                                bool spsel)
> +{
> +    /* Return a pointer to the location where we currently store the
> +     * stack pointer for the requested security state and thread mode.
> +     * This pointer will become invalid if the CPU state is updated
> +     * such that the stack pointers are switched around (eg changing
> +     * the SPSEL control bit).
> +     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
> +     * Unlike that pseudocode, we require the caller to pass us in the
> +     * SPSEL control bit value; this is because we also use this
> +     * function in handling of pushing of the callee-saves registers
> +     * part of the v8M stack frame, and in that case the SPSEL bit
> +     * comes from the exception return magic LR value.

Exception return magic lr value does not appear to match "pushing".  Did you
mean "poping" here?

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

  parent reply	other threads:[~2017-10-05 16:04 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-22 14:59 [Qemu-devel] [PATCH 00/20] ARM v8M: exception entry, exit and security Peter Maydell
2017-09-22 14:59 ` [Qemu-devel] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset Peter Maydell
2017-09-23  0:34   ` Richard Henderson
2017-09-29 21:03   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-09-22 14:59 ` [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return Peter Maydell
2017-10-05  4:44   ` Philippe Mathieu-Daudé
2017-10-05 16:04   ` Richard Henderson [this message]
2017-10-05 16:20     ` Peter Maydell
2017-10-06 13:22       ` Peter Maydell
2017-10-06 13:24         ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode Peter Maydell
2017-10-05  3:25   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:09   ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 04/20] target/arm: Restore security state on exception return Peter Maydell
2017-10-05 16:14   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register " Peter Maydell
2017-10-05 16:18   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M Peter Maydell
2017-10-05 16:25   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 07/20] target/arm: Warn about restoring to unaligned stack Peter Maydell
2017-09-29 21:05   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:28   ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M Peter Maydell
2017-09-29 21:07   ` Philippe Mathieu-Daudé
2017-10-05 16:32   ` Richard Henderson
2017-10-05 16:34     ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR Peter Maydell
2017-10-05 16:39   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 10/20] target/arm: Update excret sanity checks for v8M Peter Maydell
2017-10-05 17:16   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 11/20] target/arm: Add support for restoring v8M additional state context Peter Maydell
2017-10-05 17:30   ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 12/20] target/arm: Add v8M support to exception entry code Peter Maydell
2017-10-05 18:31   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution Unit registers Peter Maydell
2017-10-05 18:33   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 14/20] target/arm: Implement security attribute lookups for memory accesses Peter Maydell
2017-10-05 18:39   ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 15/20] target/arm: Fix calculation of secure mm_idx values Peter Maydell
2017-10-05  4:46   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:41   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 16/20] target/arm: Factor out "get mmuidx for specified security state" Peter Maydell
2017-10-05  3:29   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:42   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction Peter Maydell
2017-09-22 17:18   ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2017-10-05 18:50   ` [Qemu-devel] " Richard Henderson
2017-10-05 18:55     ` Peter Maydell
2017-10-05 18:57       ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS Peter Maydell
2017-10-05 13:07   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:56   ` [Qemu-devel] " Richard Henderson
2017-10-05 19:40     ` Peter Maydell
2017-09-22 15:00 ` [Qemu-devel] [PATCH 19/20] target/arm: Implement secure function return Peter Maydell
2017-10-05 13:11   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:00   ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit Peter Maydell
2017-10-05  4:33   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:01   ` [Qemu-devel] " Richard Henderson
2017-10-05  4:51 ` [Qemu-devel] [Qemu-arm] [PATCH 00/20] ARM v8M: exception entry, exit and security Philippe Mathieu-Daudé
2017-10-06 13:29 ` Peter Maydell

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