From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751263AbdGONGq (ORCPT ); Sat, 15 Jul 2017 09:06:46 -0400 Received: from smtp2-g21.free.fr ([212.27.42.2]:44883 "EHLO smtp2-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751187AbdGONGp (ORCPT ); Sat, 15 Jul 2017 09:06:45 -0400 Subject: Re: [RFC PATCH v2] irqchip: Add support for tango interrupt router From: Mason To: Marc Zyngier Cc: Thomas Petazzoni , Thomas Gleixner , Jason Cooper , Mark Rutland , Thibaud Cornic , LKML , Linux ARM References: <657580dd-0cfe-e377-e425-0deabf6d20c3@free.fr> <20170606175219.34ef62b9@free-electrons.com> Message-ID: Date: Sat, 15 Jul 2017 15:06:06 +0200 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:52.0) Gecko/20100101 Firefox/52.0 SeaMonkey/2.49.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/07/2017 18:39, Mason wrote: > 128 inputs, 24 outputs (to GIC SPI 0-23) > > There might be a few things wrong with this driver. When I > cat /proc/interrupts the interrupt count appears to be bogus > (as if level IRQ counts are added to edge IRQ counts). OK, I found the issue. It occurred on the interrupt lines that stay high when the HW block is idle, so I mishandled them on every level interrupt. I have two remaining issues: 1) In the ISR, I get the hwirq from the GIC. What is the API to translate that to the SPI? I'm currently just subtracting 32. 2) I'm currently using a single domain, with a handle_simple_irq domain handler. That's probably wrong. Should I define two domains, one for edge IRQs and one for level IRQs, and use the appropriate handler? Should both domain have 128 entries? (I.e. are they indexed by the hwirq?) And should I use linear or tree? Regards. From mboxrd@z Thu Jan 1 00:00:00 1970 From: slash.tmp@free.fr (Mason) Date: Sat, 15 Jul 2017 15:06:06 +0200 Subject: [RFC PATCH v2] irqchip: Add support for tango interrupt router In-Reply-To: References: <657580dd-0cfe-e377-e425-0deabf6d20c3@free.fr> <20170606175219.34ef62b9@free-electrons.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12/07/2017 18:39, Mason wrote: > 128 inputs, 24 outputs (to GIC SPI 0-23) > > There might be a few things wrong with this driver. When I > cat /proc/interrupts the interrupt count appears to be bogus > (as if level IRQ counts are added to edge IRQ counts). OK, I found the issue. It occurred on the interrupt lines that stay high when the HW block is idle, so I mishandled them on every level interrupt. I have two remaining issues: 1) In the ISR, I get the hwirq from the GIC. What is the API to translate that to the SPI? I'm currently just subtracting 32. 2) I'm currently using a single domain, with a handle_simple_irq domain handler. That's probably wrong. Should I define two domains, one for edge IRQs and one for level IRQs, and use the appropriate handler? Should both domain have 128 entries? (I.e. are they indexed by the hwirq?) And should I use linear or tree? Regards.