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From: Dave Hansen <dave.hansen@intel.com>
To: bp@alien8.de, mingo@kernel.org, linux-kernel@vger.kernel.org,
	mroos@linux.ee, hpa@zytor.com, tglx@linutronix.de,
	thomas.lendacky@amd.com, linux-tip-commits@vger.kernel.org
Subject: Re: [tip:x86/pti] x86/pti: Make sure the user/kernel PTEs match
Date: Fri, 9 Feb 2018 15:30:02 -0800	[thread overview]
Message-ID: <c1ab0e86-e7ed-6950-2b84-e6ebaa6d6db8@intel.com> (raw)
In-Reply-To: <tip-52994c256df36fda9a715697431cba9daecb6b11@git.kernel.org>

On 01/03/2018 08:22 AM, tip-bot for Thomas Gleixner wrote:
> --- a/arch/x86/mm/pti.c
> +++ b/arch/x86/mm/pti.c
> @@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void)
>  static void __init pti_clone_entry_text(void)
>  {
>  	pti_clone_pmds((unsigned long) __entry_text_start,
> -			(unsigned long) __irqentry_text_end, _PAGE_RW);
> +			(unsigned long) __irqentry_text_end,
> +		       _PAGE_RW | _PAGE_GLOBAL);
>  }

We appear to have lost all of our global bits between this and the
cpu_entry_area itself.  To make K8 happy, shouldn't we just *set*
_PAGE_GLOBAL universally instead of clearing it universally?

Also, don't we want _PAGE_GLOBAL in the cpu_entry_area.c pte setting?  I
think I had this for all the shared user/kernel areas near the end of
the KAISER era, but we appear to have totally nuked it for PTI.

  reply	other threads:[~2018-02-09 23:30 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-02 20:49 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos
2018-01-02 21:27 ` Borislav Petkov
2018-01-02 23:07   ` Thomas Gleixner
2018-01-03  9:16     ` Meelis Roos
2018-01-03 12:42       ` Borislav Petkov
2018-01-03 13:17         ` Thomas Gleixner
2018-01-03 13:17           ` Thomas Gleixner
2018-01-03 14:01           ` Meelis Roos
2018-01-03 14:01             ` mroos
2018-01-03 16:22           ` [tip:x86/pti] x86/pti: Make sure the user/kernel PTEs match tip-bot for Thomas Gleixner
2018-02-09 23:30             ` Dave Hansen [this message]
2018-02-13 15:59               ` Thomas Gleixner
2018-01-03  7:07   ` 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64 Meelis Roos

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