From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D237C433EF for ; Mon, 23 May 2022 09:08:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232644AbiEWJIR (ORCPT ); Mon, 23 May 2022 05:08:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232593AbiEWJIO (ORCPT ); Mon, 23 May 2022 05:08:14 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A3E84553B for ; Mon, 23 May 2022 02:08:10 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id v8so22504237lfd.8 for ; Mon, 23 May 2022 02:08:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=+gkruPfauVziDXLSKtJ8JdAtuSmLZSndfwFUO0C6s8M=; b=OIqnmTbbaF0wekh3DIkgvMXkfsZ/RKvvw2nH7ZxA93h5C84U43/uP9ghp7+3qzsz+Y RpySF754PkAQAcG/htzkhDCT/W4YH3wmPYxmrkC40PK2l27ItrgQ0x0F2LMO7yiI/seR zobJm0PqVPlIu4nG6Ufg5ZM3x8OpE10RD3ZCps1Kmkf0HP/tVy+ZAoybDG1F4PvSLnIv +wWG3XUilGa3txzLYRDbJ2O3O/Ws5vJ7I0oTGVcuNs5Bo/QWpchqYDEcCLG7G/OtuXR3 rb0FrHd2MIitgqbMkokhJ5riuRM6zjZNPmDlOXAbOMMaNWofU7S3NqjJTDvKAj/4fLHn H15g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=+gkruPfauVziDXLSKtJ8JdAtuSmLZSndfwFUO0C6s8M=; b=CPMmjCU4uWo+WB1fEaoPYbXN0eEPvvYDpz/jOvSPn9283OjrUo9X8TEb/s7gn5+HrK XVCVAQTEV2LXGGMU541H/uDdfkgHYxCvya7KPFbAzU7AuRdwNczeivMvKxYeiLEFzEVR Iz8cWcPfKptlKbulZnyAja2wfPdcjpH5j+YkzB5qr0D4jaxWFbNoqD+7X0Jnx2up0nPj UhPruUwDLjN+NB9W1Fdg3WStTnR+W7G0w6ZJuAvV9/zE/hQDT7WLXhVXf5R/dGOBmWA5 1KjVLPsh7jEtqtdSc4qSQqs+OWxRHwJUD9IHDcWw3bj9bHDkmJN4RakGnteYbB4n9fiV DrVA== X-Gm-Message-State: AOAM530zV9J/tMhyOXU6cSt/LcbD1LlnBYU8SO1hGwGnqxa+k9KDW1i5 PZoLWvmyE62/gF6s5I1c+Xskqw== X-Google-Smtp-Source: ABdhPJxRL0NWt1+XGIYsPk6WVUB63i+n1Q5H+fxE/7J5f8PuLiu7JgwO4ZtbHb98OoYwgXsWvyj/Zw== X-Received: by 2002:a19:674b:0:b0:477:bd37:f464 with SMTP id e11-20020a19674b000000b00477bd37f464mr15302754lfj.661.1653296888713; Mon, 23 May 2022 02:08:08 -0700 (PDT) Received: from [192.168.0.17] (78-11-189-27.static.ip.netia.com.pl. [78.11.189.27]) by smtp.gmail.com with ESMTPSA id q15-20020ac2510f000000b0047255d21124sm1873685lfb.83.2022.05.23.02.08.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 May 2022 02:08:08 -0700 (PDT) Message-ID: Date: Mon, 23 May 2022 11:08:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree Content-Language: en-US To: Tomer Maimon , avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, tglx@linutronix.de, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, jirislaby@kernel.org, shawnguo@kernel.org, bjorn.andersson@linaro.org, geert+renesas@glider.be, marcel.ziswiler@toradex.com, vkoul@kernel.org, biju.das.jz@bp.renesas.com, nobuhiro1.iwamatsu@toshiba.co.jp, robert.hancock@calian.com, j.neuschaefer@gmx.net, lkundrak@v3.sk Cc: soc@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20220522155046.260146-1-tmaimon77@gmail.com> <20220522155046.260146-18-tmaimon77@gmail.com> From: Krzysztof Kozlowski In-Reply-To: <20220522155046.260146-18-tmaimon77@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/05/2022 17:50, Tomer Maimon wrote: > This adds initial device tree support for the > Nuvoton NPCM845 Board Management controller (BMC) SoC family. Thank you for your patch. There is something to discuss/improve. > > The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and > have various peripheral IPs. > > Signed-off-by: Tomer Maimon > --- > arch/arm64/boot/dts/Makefile | 1 + > .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 197 ++++++++++++++++++ > .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 77 +++++++ > 3 files changed, 275 insertions(+) > create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi > create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi > > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 1ba04e31a438..7b107fa7414b 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -19,6 +19,7 @@ subdir-y += lg > subdir-y += marvell > subdir-y += mediatek > subdir-y += microchip > +subdir-y += nuvoton > subdir-y += nvidia > subdir-y += qcom > subdir-y += realtek > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi > new file mode 100644 > index 000000000000..19c672ecfee7 > --- /dev/null > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi > @@ -0,0 +1,197 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com > + > +#include > +#include > +#include > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + > + /* external reference clock */ > + clk_refclk: clk-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000> This is not a property of a SoC, but board. > + clock-output-names = "refclk"; > + }; > + > + /* external reference clock for cpu. float in normal operation */ > + clk_sysbypck: clk-sysbypck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <1000000000>; This is not a property of a SoC, but board. > + clock-output-names = "sysbypck"; > + }; > + > + /* external reference clock for MC. float in normal operation */ > + clk_mcbypck: clk-mcbypck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <1050000000>; This is not a property of a SoC, but board. > + clock-output-names = "mcbypck"; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges; > + > + gcr: gcr@f0800000 { Generic node names. I guess it is system-controller? > + compatible = "nuvoton,npcm845-gcr", "syscon", > + "simple-mfd"; > + reg = <0x0 0xf0800000 0x0 0x1000>; > + }; > + > + gic: interrupt-controller@dfff9000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xdfff9000 0x0 0x1000>, > + <0x0 0xdfffa000 0x0 0x2000>, > + <0x0 0xdfffc000 0x0 0x2000>, > + <0x0 0xdfffe000 0x0 0x2000>; > + interrupts = ; > + #interrupt-cells = <3>; > + interrupt-controller; > + #address-cells = <0>; > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + }; > + }; > + }; > + > + ahb { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges; > + > + rstc: rstc@f0801000 { Generic node names. > + compatible = "nuvoton,npcm845-reset"; > + reg = <0x0 0xf0801000 0x0 0x78>; > + #reset-cells = <2>; > + syscon = <&gcr>; > + }; > + > + clk: clock-controller@f0801000 { > + compatible = "nuvoton,npcm845-clk"; > + #clock-cells = <1>; > + reg = <0x0 0xf0801000 0x0 0x1000>; > + clock-names = "refclk", "sysbypck", "mcbypck"; > + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; > + }; > + > + apb { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges = <0x0 0x0 0xf0000000 0x00300000>, > + <0xfff00000 0x0 0xfff00000 0x00016000>; > + > + timer0: timer@8000 { > + compatible = "nuvoton,npcm845-timer"; > + interrupts = ; > + reg = <0x8000 0x1C>; > + clocks = <&clk_refclk>; > + clock-names = "refclk"; > + }; > + > + serial0: serial@0 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x0 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial1: serial@1000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x1000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial2: serial@2000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x2000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial3: serial@3000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x3000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial4: serial@4000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x4000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial5: serial@5000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x5000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial6: serial@6000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x6000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + watchdog0: watchdog@801c { > + compatible = "nuvoton,npcm845-wdt"; > + interrupts = ; > + reg = <0x801c 0x4>; > + status = "disabled"; > + clocks = <&clk_refclk>; > + syscon = <&gcr>; > + }; > + > + watchdog1: watchdog@901c { > + compatible = "nuvoton,npcm845-wdt"; > + interrupts = ; > + reg = <0x901c 0x4>; > + status = "disabled"; > + clocks = <&clk_refclk>; > + syscon = <&gcr>; > + }; > + > + watchdog2: watchdog@a01c { > + compatible = "nuvoton,npcm845-wdt"; > + interrupts = ; > + reg = <0xa01c 0x4>; > + status = "disabled"; > + clocks = <&clk_refclk>; > + syscon = <&gcr>; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi > new file mode 100644 > index 000000000000..900cee112251 > --- /dev/null > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi > @@ -0,0 +1,77 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com > + > +#include "nuvoton-common-npcm8xx.dtsi" > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; You do not have gic here, so it's not correct. Do not reference nodes outsides of the file. > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + clocks = <&clk NPCM8XX_CLK_CPU>; > + reg = <0x0 0x0>; Why do you have two address cells? A bit more complicated and not necessary, I think. > + next-level-cache = <&l2>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + clocks = <&clk NPCM8XX_CLK_CPU>; > + reg = <0x0 0x1>; > + next-level-cache = <&l2>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + clocks = <&clk NPCM8XX_CLK_CPU>; > + reg = <0x0 0x2>; > + next-level-cache = <&l2>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + clocks = <&clk NPCM8XX_CLK_CPU>; > + reg = <0x0 0x3>; > + next-level-cache = <&l2>; > + enable-method = "psci"; > + }; > + > + l2: l2-cache { > + compatible = "cache"; Is this a real compatible? What bindings are you using here? > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a35-pmu"; > + interrupts = , > + , > + , > + ; > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; Weird indentation. > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > +}; Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDA9CC433F5 for ; Mon, 23 May 2022 10:25:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dDlFRQ6Wvx8fac+0UGmCv9Q5oBJecIPIOXqJ7CqaLYA=; b=sqHBPpyms8YaGz aPBWg+u1DltsuR6BTKjoi2ginJZzV2P6dBvTclYqOd8DAbD/pSlyikSdd1crhUacqdnwajgwpJ/UM duRpXS3cy3ZfNr+rTWGBAa5tGkOf1+4CQOVmwYSEgrep3sp1wD9+UV4CBMWlFJYX9fUvBLKhG5Jr8 Rim/zjHrTuWXX/mw+XvTE4+z/mzeBXm1Nl/EkMhccYI5nS17VQ/7H0Vi0B4DW7CrYsb8kL8/0uPEs kk9afzU3wwp1BwFFvvuBURYztziy0Mg/HoDHEor9Fm9MGqSvwDDHTQwSustR78YHUwPJBx7ZdrFo5 lQ+1rS+klzHnXqDBOx/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt5Dc-003Cqh-Lc; Mon, 23 May 2022 10:23:22 +0000 Received: from mail-lf1-x12d.google.com ([2a00:1450:4864:20::12d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt42u-002i5D-9n for linux-arm-kernel@lists.infradead.org; Mon, 23 May 2022 09:08:14 +0000 Received: by mail-lf1-x12d.google.com with SMTP id u23so24452749lfc.1 for ; Mon, 23 May 2022 02:08:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=+gkruPfauVziDXLSKtJ8JdAtuSmLZSndfwFUO0C6s8M=; b=OIqnmTbbaF0wekh3DIkgvMXkfsZ/RKvvw2nH7ZxA93h5C84U43/uP9ghp7+3qzsz+Y RpySF754PkAQAcG/htzkhDCT/W4YH3wmPYxmrkC40PK2l27ItrgQ0x0F2LMO7yiI/seR zobJm0PqVPlIu4nG6Ufg5ZM3x8OpE10RD3ZCps1Kmkf0HP/tVy+ZAoybDG1F4PvSLnIv +wWG3XUilGa3txzLYRDbJ2O3O/Ws5vJ7I0oTGVcuNs5Bo/QWpchqYDEcCLG7G/OtuXR3 rb0FrHd2MIitgqbMkokhJ5riuRM6zjZNPmDlOXAbOMMaNWofU7S3NqjJTDvKAj/4fLHn H15g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=+gkruPfauVziDXLSKtJ8JdAtuSmLZSndfwFUO0C6s8M=; b=yY/Yiwq/9pJEWsGT2f8OAxsQ8blI7FbIGTfuxb/f99Glfc91yRuP/jBRQHMYuumXik 6gGVJqkHMw8TZ20ClwOMi1nOduEnUxb0ULoODqMQugOox1z1Cf5ARNubEKUHWIKY2Vmf LfvqEmRI0nJr/fJc2rMd4G8FXl4+47P5MRo6x/yBd6wPujzTPBnjxc/BI4RORauhdIyD i4QnxYis0jISLBpK4sg8eAtp7GNlNo9SYMqEEkBGLCBHBcRJ3GjEYZH9+b82LDbNvDCd lxuapnxoMfA+D5q7i5brrCCOFoSk+UWm3WI3ZUwHdzzh/JW12TlKK6kWzZpKpgAgL9Zo TnjA== X-Gm-Message-State: AOAM531zEP4LUYLmeMtEFPZ/d0YaHVY87FiEv8darrZo/HRdfGl2c6Sa h9H4V7utIF8VPf2Nlq31HF7HIQ== X-Google-Smtp-Source: ABdhPJxRL0NWt1+XGIYsPk6WVUB63i+n1Q5H+fxE/7J5f8PuLiu7JgwO4ZtbHb98OoYwgXsWvyj/Zw== X-Received: by 2002:a19:674b:0:b0:477:bd37:f464 with SMTP id e11-20020a19674b000000b00477bd37f464mr15302754lfj.661.1653296888713; Mon, 23 May 2022 02:08:08 -0700 (PDT) Received: from [192.168.0.17] (78-11-189-27.static.ip.netia.com.pl. [78.11.189.27]) by smtp.gmail.com with ESMTPSA id q15-20020ac2510f000000b0047255d21124sm1873685lfb.83.2022.05.23.02.08.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 May 2022 02:08:08 -0700 (PDT) Message-ID: Date: Mon, 23 May 2022 11:08:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device tree Content-Language: en-US To: Tomer Maimon , avifishman70@gmail.com, tali.perry1@gmail.com, joel@jms.id.au, venture@google.com, yuenn@google.com, benjaminfair@google.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, daniel.lezcano@linaro.org, tglx@linutronix.de, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, jirislaby@kernel.org, shawnguo@kernel.org, bjorn.andersson@linaro.org, geert+renesas@glider.be, marcel.ziswiler@toradex.com, vkoul@kernel.org, biju.das.jz@bp.renesas.com, nobuhiro1.iwamatsu@toshiba.co.jp, robert.hancock@calian.com, j.neuschaefer@gmx.net, lkundrak@v3.sk Cc: soc@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-serial@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20220522155046.260146-1-tmaimon77@gmail.com> <20220522155046.260146-18-tmaimon77@gmail.com> From: Krzysztof Kozlowski In-Reply-To: <20220522155046.260146-18-tmaimon77@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_020812_402581_331EEFEE X-CRM114-Status: GOOD ( 22.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 22/05/2022 17:50, Tomer Maimon wrote: > This adds initial device tree support for the > Nuvoton NPCM845 Board Management controller (BMC) SoC family. Thank you for your patch. There is something to discuss/improve. > > The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and > have various peripheral IPs. > > Signed-off-by: Tomer Maimon > --- > arch/arm64/boot/dts/Makefile | 1 + > .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 197 ++++++++++++++++++ > .../boot/dts/nuvoton/nuvoton-npcm845.dtsi | 77 +++++++ > 3 files changed, 275 insertions(+) > create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi > create mode 100644 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi > > diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile > index 1ba04e31a438..7b107fa7414b 100644 > --- a/arch/arm64/boot/dts/Makefile > +++ b/arch/arm64/boot/dts/Makefile > @@ -19,6 +19,7 @@ subdir-y += lg > subdir-y += marvell > subdir-y += mediatek > subdir-y += microchip > +subdir-y += nuvoton > subdir-y += nvidia > subdir-y += qcom > subdir-y += realtek > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi > new file mode 100644 > index 000000000000..19c672ecfee7 > --- /dev/null > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi > @@ -0,0 +1,197 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com > + > +#include > +#include > +#include > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + > + /* external reference clock */ > + clk_refclk: clk-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000> This is not a property of a SoC, but board. > + clock-output-names = "refclk"; > + }; > + > + /* external reference clock for cpu. float in normal operation */ > + clk_sysbypck: clk-sysbypck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <1000000000>; This is not a property of a SoC, but board. > + clock-output-names = "sysbypck"; > + }; > + > + /* external reference clock for MC. float in normal operation */ > + clk_mcbypck: clk-mcbypck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <1050000000>; This is not a property of a SoC, but board. > + clock-output-names = "mcbypck"; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges; > + > + gcr: gcr@f0800000 { Generic node names. I guess it is system-controller? > + compatible = "nuvoton,npcm845-gcr", "syscon", > + "simple-mfd"; > + reg = <0x0 0xf0800000 0x0 0x1000>; > + }; > + > + gic: interrupt-controller@dfff9000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xdfff9000 0x0 0x1000>, > + <0x0 0xdfffa000 0x0 0x2000>, > + <0x0 0xdfffc000 0x0 0x2000>, > + <0x0 0xdfffe000 0x0 0x2000>; > + interrupts = ; > + #interrupt-cells = <3>; > + interrupt-controller; > + #address-cells = <0>; > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + }; > + }; > + }; > + > + ahb { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges; > + > + rstc: rstc@f0801000 { Generic node names. > + compatible = "nuvoton,npcm845-reset"; > + reg = <0x0 0xf0801000 0x0 0x78>; > + #reset-cells = <2>; > + syscon = <&gcr>; > + }; > + > + clk: clock-controller@f0801000 { > + compatible = "nuvoton,npcm845-clk"; > + #clock-cells = <1>; > + reg = <0x0 0xf0801000 0x0 0x1000>; > + clock-names = "refclk", "sysbypck", "mcbypck"; > + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; > + }; > + > + apb { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges = <0x0 0x0 0xf0000000 0x00300000>, > + <0xfff00000 0x0 0xfff00000 0x00016000>; > + > + timer0: timer@8000 { > + compatible = "nuvoton,npcm845-timer"; > + interrupts = ; > + reg = <0x8000 0x1C>; > + clocks = <&clk_refclk>; > + clock-names = "refclk"; > + }; > + > + serial0: serial@0 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x0 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial1: serial@1000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x1000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial2: serial@2000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x2000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial3: serial@3000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x3000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial4: serial@4000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x4000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial5: serial@5000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x5000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial6: serial@6000 { > + compatible = "nuvoton,npcm845-uart"; > + reg = <0x6000 0x1000>; > + clocks = <&clk NPCM8XX_CLK_UART>; > + interrupts = ; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + watchdog0: watchdog@801c { > + compatible = "nuvoton,npcm845-wdt"; > + interrupts = ; > + reg = <0x801c 0x4>; > + status = "disabled"; > + clocks = <&clk_refclk>; > + syscon = <&gcr>; > + }; > + > + watchdog1: watchdog@901c { > + compatible = "nuvoton,npcm845-wdt"; > + interrupts = ; > + reg = <0x901c 0x4>; > + status = "disabled"; > + clocks = <&clk_refclk>; > + syscon = <&gcr>; > + }; > + > + watchdog2: watchdog@a01c { > + compatible = "nuvoton,npcm845-wdt"; > + interrupts = ; > + reg = <0xa01c 0x4>; > + status = "disabled"; > + clocks = <&clk_refclk>; > + syscon = <&gcr>; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi > new file mode 100644 > index 000000000000..900cee112251 > --- /dev/null > +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi > @@ -0,0 +1,77 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com > + > +#include "nuvoton-common-npcm8xx.dtsi" > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; You do not have gic here, so it's not correct. Do not reference nodes outsides of the file. > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + clocks = <&clk NPCM8XX_CLK_CPU>; > + reg = <0x0 0x0>; Why do you have two address cells? A bit more complicated and not necessary, I think. > + next-level-cache = <&l2>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + clocks = <&clk NPCM8XX_CLK_CPU>; > + reg = <0x0 0x1>; > + next-level-cache = <&l2>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + clocks = <&clk NPCM8XX_CLK_CPU>; > + reg = <0x0 0x2>; > + next-level-cache = <&l2>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + clocks = <&clk NPCM8XX_CLK_CPU>; > + reg = <0x0 0x3>; > + next-level-cache = <&l2>; > + enable-method = "psci"; > + }; > + > + l2: l2-cache { > + compatible = "cache"; Is this a real compatible? What bindings are you using here? > + }; > + }; > + > + arm-pmu { > + compatible = "arm,cortex-a35-pmu"; > + interrupts = , > + , > + , > + ; > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; Weird indentation. > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > +}; Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel