From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-f50.google.com ([74.125.83.50]:40475 "EHLO mail-pg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751219AbdLCN4g (ORCPT ); Sun, 3 Dec 2017 08:56:36 -0500 Subject: Invalidation in SMMU v3 To: Jean-Philippe Brucker , "iommu@lists.linux-foundation.org" , "kvm@vger.kernel.org" , linux-pci References: <52a6fdbb-9a47-76c0-da59-89ac561b8ee3@gmail.com> <8fd78f56-43ed-e480-1c98-5d1162452674@arm.com> Cc: Alex Williamson , "kevin.tian@intel.com" From: valmiki Message-ID: Date: Sun, 3 Dec 2017 19:26:31 +0530 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Sender: linux-pci-owner@vger.kernel.org List-ID: Hi Jean, In PASID flow arm_smmu_atc_inv_master_all is called where size and iova of arm_smmu_atc_inv_to_cmd are zero and no address is being filled in struct arm_smmu_cmdq_ent->atc.addr. So how will smmu hardware know if there are any ats translations requested or not ? How invalidation are carried out in PASID flow w.r.t address and size? Regards, Valmiki --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus From mboxrd@z Thu Jan 1 00:00:00 1970 From: valmiki Subject: Invalidation in SMMU v3 Date: Sun, 3 Dec 2017 19:26:31 +0530 Message-ID: References: <52a6fdbb-9a47-76c0-da59-89ac561b8ee3@gmail.com> <8fd78f56-43ed-e480-1c98-5d1162452674@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit To: Jean-Philippe Brucker , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , "kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , linux-pci Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org List-Id: kvm.vger.kernel.org Hi Jean, In PASID flow arm_smmu_atc_inv_master_all is called where size and iova of arm_smmu_atc_inv_to_cmd are zero and no address is being filled in struct arm_smmu_cmdq_ent->atc.addr. So how will smmu hardware know if there are any ats translations requested or not ? How invalidation are carried out in PASID flow w.r.t address and size? Regards, Valmiki --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus