From: Paolo Bonzini <pbonzini@redhat.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v6 11/11] [PATCH v6] QEMU
Date: Wed, 2 May 2018 18:19:25 +0200 [thread overview]
Message-ID: <c2d9b2d7-ef92-3553-3df9-9c2a6b85d92c@redhat.com> (raw)
In-Reply-To: <20180426234831.832090725@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 7593 bytes --]
On 27/04/2018 01:48, speck for konrad.wilk_at_oracle.com wrote:
>
>
> i386: Add bit(2) of SPEC_CTRL MSR support - Reduced Data Speculation
>
> Now users can do:
>
> cpu host,+spec-ctrl,+rds
>
> to have both IBRS and RDS support.
>
> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
> ---
>
> v3: s/ssb/rds/
> v4: s/spec_store_bypass/rds/
> s/MDD/Reduced Data Speculation/
>
> target/i386/cpu.c | 22 +++++++++++-----------
> target/i386/cpu.h | 1 +
> 2 files changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 39e791f..6256e48 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -459,7 +459,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> NULL, NULL, NULL, NULL,
> NULL, NULL, NULL, NULL,
> NULL, NULL, "spec-ctrl", NULL,
> - NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, "rds",
> },
> .cpuid_eax = 7,
> .cpuid_needs_ecx = true, .cpuid_ecx = 0,
On closer look, everything below this line unfortunately breaks live
migration across QEMU releases.
One possibility is just to remove it.
A second one is to add more CPU models, but it is not really a good idea
as it is backporting nightmare and a substantial churn for little gain.
(In fact, it was done for Spectrev2 only because at the time OpenStack
didn't support adding individual CPU bits to virtual machines. It turns
out that some CPU models lacked PCID, because back in the day it was a
feature reserved for server SKUs only, and this caused Meltdown-enabled
kernels to crawl. Fortunately this caused OpenStack to cave in and add
support for individual CPU bits, so we don't have the issue anymore).
Finally, a third possibility is to add compatibility code for older
versions of QEMU: create machine types pc-i440fx-2.13 and pc-q35-2.13,
add a PC_COMPAT_2_12 macro in include/hw/i386/pc.h that disables RDS,
and leave the bits in the CPU models as you've down below.
Paolo
> @@ -1096,7 +1096,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_8000_0001_EDX] =
> CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
> .features[FEAT_8000_0001_ECX] =
> @@ -1152,7 +1152,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_LAHF_LM,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_6_EAX] =
> CPUID_6_EAX_ARAT,
> .xlevel = 0x80000008,
> @@ -1214,7 +1214,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_LAHF_LM,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_XSAVE] =
> CPUID_XSAVE_XSAVEOPT,
> .features[FEAT_6_EAX] =
> @@ -1284,7 +1284,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_LAHF_LM,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_XSAVE] =
> CPUID_XSAVE_XSAVEOPT,
> .features[FEAT_6_EAX] =
> @@ -1354,7 +1354,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_7_0_EBX] =
> CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> @@ -1429,7 +1429,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_7_0_EBX] =
> CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> @@ -1506,7 +1506,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_7_0_EBX] =
> CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> @@ -1584,7 +1584,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_7_0_EBX] =
> CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> @@ -1669,7 +1669,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_7_0_EBX] =
> CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> @@ -1764,7 +1764,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .features[FEAT_8000_0001_ECX] =
> CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
> .features[FEAT_7_0_EDX] =
> - CPUID_7_0_EDX_SPEC_CTRL,
> + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_RDS,
> .features[FEAT_7_0_EBX] =
> CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 2d71bc9..ff604cd 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -650,6 +650,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
> #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
> #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
> +#define CPUID_7_0_EDX_SPEC_CTRL_RDS (1U << 31) /* Reduced Data Speculation */
>
> #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
>
> --
> 1.8.3.1
>
>
prev parent reply other threads:[~2018-05-02 16:19 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-26 23:48 [MODERATED] [PATCH v6 11/11] [PATCH v6] QEMU konrad.wilk
2018-05-02 16:19 ` Paolo Bonzini [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c2d9b2d7-ef92-3553-3df9-9c2a6b85d92c@redhat.com \
--to=pbonzini@redhat.com \
--cc=speck@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.