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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id z184sm8185018wmg.7.2021.01.28.16.56.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Jan 2021 16:56:59 -0800 (PST) Subject: Re: [PATCH] usb: dwc3: gadget: Init only available HW eps To: Felipe Balbi , Thinh Nguyen , Greg Kroah-Hartman , "linux-usb@vger.kernel.org" Cc: John Youn , "stable@vger.kernel.org" References: <3080c0452df14d510d24471ce0f9bb7592cdfd4d.1609866964.git.Thinh.Nguyen@synopsys.com> <87eeiycxld.fsf@kernel.org> <75d63bab-1cdc-737e-8ae2-64e0ddeeef75@synopsys.com> <87k0spay6z.fsf@kernel.org> <19b685a9-0c25-9b6c-ecaf-ffca4069182b@synopsys.com> <87eeivwrb9.fsf@kernel.org> From: Bryan O'Donoghue Message-ID: Date: Fri, 29 Jan 2021 00:58:19 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.3 MIME-Version: 1.0 In-Reply-To: <87eeivwrb9.fsf@kernel.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On 08/01/2021 12:23, Felipe Balbi wrote: > > Hi, > > Thinh Nguyen writes: >>>>>> How have you verified this patch? Did you read Bryan's commit log? This >>>>>> is likely to reintroduce the problem raised by Bryan. >>>>>> >>>>> We verified with our FPGA HAPS with various number of endpoints. No >>>>> issue is seen. >>>> That's cool. Could you please make sure our understanding of this is >>>> sound and won't interfere with any designs? If we modify this part of >>>> the code again, I'd like to see a clear reference to a specific section >>>> of the databook detailing the expected behavior :-) >>>> >>>> cheers >>>> >>> Hm... I didn't consider bidirection endpoint other than control endpoint. >>> >>> DWC3_USB3x_NUM_EPS specifies the number of device mode for single >>> directional endpoints. A bidirectional endpoint needs 2 single >>> directional endpoints, 1 IN and 1 OUT. So, if your setup uses 3 >>> bidirection endpoints and only those, DWC3_USB3x_NUM_EPS should be 6. >>> DWC3_USB3x_NUM_IN_EPS specifies the maximum number of IN endpoint active >>> at any time. >>> >>> However, I will have to double check and confirm internally regarding >>> how to determine many endpoint would be available if bidirection >>> endpoints come into play. >>> >>> Thanks for pointing this out. Will get back on this. >>> >>> Thinh >>> >> >> Ok. Just had some discussion internally. So, like you said, any endpoint >> can be configured in either direction. However, we are limited to >> configuring up to DWC_USB3x_NUM_IN_EPS because each IN endpoint has its >> own TxFIFO while for OUT, they share the same RxFIFO. So we could have >> up to DWC_USB3x_NUM_EPS number of OUT endpoints. So, the issue Bryan >> attempted to address is still there. >> >> However, the current code still has some assumption on the number of IN >> and OUT endpoints, I need to think of a better solution. > > Yes, the assumption still exists because at the time there was no better > solution :-) > Just found this now. The commit log is too wordy. You can configure the RTL so that every endpoint can be either direction. So DWC_USB3_NUM == DWC_USB3_NUM_IN_EPS The old code was predicated on the notion the RTL was configured with EP0 IN/OUT basically fixed. In practice this _should_ be the case but the RTL does not enforce it and yes this appears in a real SoC from Imagination. --- bod