From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8057C2BB85 for ; Thu, 16 Apr 2020 09:35:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D153C21BE5 for ; Thu, 16 Apr 2020 09:35:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2503860AbgDPJfo (ORCPT ); Thu, 16 Apr 2020 05:35:44 -0400 Received: from mga12.intel.com ([192.55.52.136]:43263 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2503787AbgDPJfd (ORCPT ); Thu, 16 Apr 2020 05:35:33 -0400 IronPort-SDR: FaOqx3gjHusiIA7aLJig4pR7+mOB0+oesPCHSTLjldh5LEUDLnD37H5S3l1Gs/de7oyTpQA57F 9p/Bk4HRrcew== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2020 02:35:32 -0700 IronPort-SDR: xTBdCFZ+AyNj7x+sI6oWf2cORZqbOuteXGFH1D7+A8fhQKnjpK5phcfYqEG1bS0ATPkjdpf+ub aTAjF3ZJiA6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,390,1580803200"; d="scan'208";a="242595587" Received: from linux.intel.com ([10.54.29.200]) by orsmga007.jf.intel.com with ESMTP; 16 Apr 2020 02:35:32 -0700 Received: from [10.255.154.239] (vramuthx-MOBL1.gar.corp.intel.com [10.255.154.239]) by linux.intel.com (Postfix) with ESMTP id 3F5C05803E3; Thu, 16 Apr 2020 02:35:28 -0700 (PDT) Subject: Re: [PATCH v1 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC To: Martin Blumenstingl Cc: anders.roxell@linaro.org, andriy.shevchenko@intel.com, arnd@arndb.de, boris.brezillon@collabora.com, brendanhiggins@google.com, cheol.yong.kim@intel.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, masonccyang@mxic.com.tw, miquel.raynal@bootlin.com, piotrs@cadence.com, qi-ming.wu@intel.com, richard@nod.at, robh+dt@kernel.org, tglx@linutronix.de, vigneshr@ti.com References: <20200414022433.36622-3-vadivel.muruganx.ramuthevar@linux.intel.com> <20200415220533.733834-1-martin.blumenstingl@googlemail.com> From: "Ramuthevar, Vadivel MuruganX" Message-ID: Date: Thu, 16 Apr 2020 17:35:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200415220533.733834-1-martin.blumenstingl@googlemail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin,     Thank you so much for review comments and your time... On 16/4/2020 6:05 am, Martin Blumenstingl wrote: > Hi, > > first of all: thank you for working on upstreaming this. > Especially since you are going to use the new exec_op style in v2 as > Boris suggested. > >> From: Ramuthevar Vadivel Murugan >> >> This patch adds the new IP of Nand Flash Controller(NFC) support >> on Intel's Lightning Mountain(LGM) SoC. >> >> DMA is used for burst data transfer operation, also DMA HW supports >> aligned 32bit memory address and aligned data access by default. >> DMA burst of 8 supported. Data register used to support the read/write >> operation from/to device. > I am wondering how this new hardware is different from the Lantiq NAND > controller IP - for which there is already a driver in mainline (it's > in drivers/mtd/nand/raw/xway_nand.c). > The CON and WAIT registers look suspiciously similar. > > As far as I understand the "old" SoCs (VRX200 and earlier) don't have > a built-in ECC engine. This seems to have changed with ARX300 though > (again, AFAIK). > > A bit of lineage on these SoCs (initially these were developed by > Infineon. Lantiq then started as an Infineon spin-off in 2009 and > was then acquired by Intel in 2015): > - Danube > - ARX100 from 2008/2009 > - VRX200 from 2009/2010 > - ARX300 from 2014 > - GRX350 from 2015/2016 > - GRX550 from 2017 > - and now finally: LGM from 2020 (est.) > > The existing xway_nand driver supports the Danube, ARX100 and VRX200 > SoCs. Lantiq upstreamed a driver for an older version of this IP core 8 years ago, see here: https://elixir.bootlin.com/linux/v5.5.6/source/drivers/mtd/nand/raw/xway_nand.c It does not support DMA and ECC. This upstream driver works with the xrx200, I do not know how well it works with other SoCs. Regards Vadivel > > > Best regards, > Martin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C256C352BE for ; Thu, 16 Apr 2020 09:35:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C75F21BE5 for ; Thu, 16 Apr 2020 09:35:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fQOywyGI" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1C75F21BE5 Authentication-Results: mail.kernel.org; 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16 Apr 2020 02:35:32 -0700 Received: from [10.255.154.239] (vramuthx-MOBL1.gar.corp.intel.com [10.255.154.239]) by linux.intel.com (Postfix) with ESMTP id 3F5C05803E3; Thu, 16 Apr 2020 02:35:28 -0700 (PDT) Subject: Re: [PATCH v1 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC To: Martin Blumenstingl References: <20200414022433.36622-3-vadivel.muruganx.ramuthevar@linux.intel.com> <20200415220533.733834-1-martin.blumenstingl@googlemail.com> From: "Ramuthevar, Vadivel MuruganX" Message-ID: Date: Thu, 16 Apr 2020 17:35:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200415220533.733834-1-martin.blumenstingl@googlemail.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200416_023536_367231_9C2A8145 X-CRM114-Status: GOOD ( 16.44 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org, qi-ming.wu@intel.com, anders.roxell@linaro.org, andriy.shevchenko@intel.com, arnd@arndb.de, vigneshr@ti.com, richard@nod.at, brendanhiggins@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, tglx@linutronix.de, masonccyang@mxic.com.tw, piotrs@cadence.com Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgTWFydGluLAoKIMKgwqDCoCBUaGFuayB5b3Ugc28gbXVjaCBmb3IgcmV2aWV3IGNvbW1lbnRz IGFuZCB5b3VyIHRpbWUuLi4KCk9uIDE2LzQvMjAyMCA2OjA1IGFtLCBNYXJ0aW4gQmx1bWVuc3Rp bmdsIHdyb3RlOgo+IEhpLAo+Cj4gZmlyc3Qgb2YgYWxsOiB0aGFuayB5b3UgZm9yIHdvcmtpbmcg b24gdXBzdHJlYW1pbmcgdGhpcy4KPiBFc3BlY2lhbGx5IHNpbmNlIHlvdSBhcmUgZ29pbmcgdG8g dXNlIHRoZSBuZXcgZXhlY19vcCBzdHlsZSBpbiB2MiBhcwo+IEJvcmlzIHN1Z2dlc3RlZC4KPgo+ PiBGcm9tOiBSYW11dGhldmFyIFZhZGl2ZWwgTXVydWdhbiA8dmFkaXZlbC5tdXJ1Z2FueC5yYW11 dGhldmFyQGxpbnV4LmludGVsLmNvbT4KPj4KPj4gVGhpcyBwYXRjaCBhZGRzIHRoZSBuZXcgSVAg b2YgTmFuZCBGbGFzaCBDb250cm9sbGVyKE5GQykgc3VwcG9ydAo+PiBvbiBJbnRlbCdzIExpZ2h0 bmluZyBNb3VudGFpbihMR00pIFNvQy4KPj4KPj4gRE1BIGlzIHVzZWQgZm9yIGJ1cnN0IGRhdGEg dHJhbnNmZXIgb3BlcmF0aW9uLCBhbHNvIERNQSBIVyBzdXBwb3J0cwo+PiBhbGlnbmVkIDMyYml0 IG1lbW9yeSBhZGRyZXNzIGFuZCBhbGlnbmVkIGRhdGEgYWNjZXNzIGJ5IGRlZmF1bHQuCj4+IERN QSBidXJzdCBvZiA4IHN1cHBvcnRlZC4gRGF0YSByZWdpc3RlciB1c2VkIHRvIHN1cHBvcnQgdGhl IHJlYWQvd3JpdGUKPj4gb3BlcmF0aW9uIGZyb20vdG8gZGV2aWNlLgo+IEkgYW0gd29uZGVyaW5n IGhvdyB0aGlzIG5ldyBoYXJkd2FyZSBpcyBkaWZmZXJlbnQgZnJvbSB0aGUgTGFudGlxIE5BTkQK PiBjb250cm9sbGVyIElQIC0gZm9yIHdoaWNoIHRoZXJlIGlzIGFscmVhZHkgYSBkcml2ZXIgaW4g bWFpbmxpbmUgKGl0J3MKPiBpbiBkcml2ZXJzL210ZC9uYW5kL3Jhdy94d2F5X25hbmQuYykuCj4g VGhlIENPTiBhbmQgV0FJVCByZWdpc3RlcnMgbG9vayBzdXNwaWNpb3VzbHkgc2ltaWxhci4KPgo+ IEFzIGZhciBhcyBJIHVuZGVyc3RhbmQgdGhlICJvbGQiIFNvQ3MgKFZSWDIwMCBhbmQgZWFybGll cikgZG9uJ3QgaGF2ZQo+IGEgYnVpbHQtaW4gRUNDIGVuZ2luZS4gVGhpcyBzZWVtcyB0byBoYXZl IGNoYW5nZWQgd2l0aCBBUlgzMDAgdGhvdWdoCj4gKGFnYWluLCBBRkFJSykuCj4KPiBBIGJpdCBv ZiBsaW5lYWdlIG9uIHRoZXNlIFNvQ3MgKGluaXRpYWxseSB0aGVzZSB3ZXJlIGRldmVsb3BlZCBi eQo+IEluZmluZW9uLiBMYW50aXEgdGhlbiBzdGFydGVkIGFzIGFuIEluZmluZW9uIHNwaW4tb2Zm IGluIDIwMDkgYW5kCj4gd2FzIHRoZW4gYWNxdWlyZWQgYnkgSW50ZWwgaW4gMjAxNSk6Cj4gLSBE YW51YmUKPiAtIEFSWDEwMCBmcm9tIDIwMDgvMjAwOQo+IC0gVlJYMjAwIGZyb20gMjAwOS8yMDEw Cj4gLSBBUlgzMDAgZnJvbSAyMDE0Cj4gLSBHUlgzNTAgZnJvbSAyMDE1LzIwMTYKPiAtIEdSWDU1 MCBmcm9tIDIwMTcKPiAtIGFuZCBub3cgZmluYWxseTogTEdNIGZyb20gMjAyMCAoZXN0LikKPgo+ IFRoZSBleGlzdGluZyB4d2F5X25hbmQgZHJpdmVyIHN1cHBvcnRzIHRoZSBEYW51YmUsIEFSWDEw MCBhbmQgVlJYMjAwCj4gU29Dcy4KTGFudGlxIHVwc3RyZWFtZWQgYSBkcml2ZXIgZm9yIGFuIG9s ZGVyIHZlcnNpb24gb2YgdGhpcyBJUCBjb3JlIDggeWVhcnMgCmFnbywgc2VlIGhlcmU6Cmh0dHBz Oi8vZWxpeGlyLmJvb3RsaW4uY29tL2xpbnV4L3Y1LjUuNi9zb3VyY2UvZHJpdmVycy9tdGQvbmFu ZC9yYXcveHdheV9uYW5kLmMgCkl0IGRvZXMgbm90IHN1cHBvcnQgRE1BIGFuZCBFQ0MuClRoaXMg dXBzdHJlYW0gZHJpdmVyIHdvcmtzIHdpdGggdGhlIHhyeDIwMCwgSSBkbyBub3Qga25vdyBob3cg d2VsbCBpdCAKd29ya3Mgd2l0aCBvdGhlciBTb0NzLgoKUmVnYXJkcwpWYWRpdmVsCj4KPgo+IEJl c3QgcmVnYXJkcywKPiBNYXJ0aW4KCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwpMaW51eCBNVEQgZGlzY3Vzc2lvbiBtYWlsaW5nIGxpc3QKaHR0 cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1tdGQvCg==