From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45F07C6FA82 for ; Thu, 22 Sep 2022 05:18:45 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2C25484C9D; Thu, 22 Sep 2022 07:18:43 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1663823923; bh=niT5a/bfk6h9aM99/aEQs6w7DC2Sltk7nrO4Y3BvH7w=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=RbvsKbqgr4EYrEec7FoGEYOf0eFYckTldK3Da5iXaSN8CB+meuNyZpEERl+S0Yd/V YpqudJr7F+zLNZeiqwp0nmNVb0bG0jz4NCezk5MC3m2o1IQo1ZE0m4AZQQ3C22Fy6a 0lPtaz9I9WkmzFC19bQxASWbsbvynW4JvuC8PGs7rnJEZwfPXWUXMXWKMqE3+rZ1+H 0SmxOzAgxWDIyLf4/sk92UfISfxHDrcwBmO+JLlHeW19afffqIX5hwqhyYQIL9ZSIL sqUexfNvgRzbVbiljR4Pe8+KykOyq60UlmJmxachx2gueD625CriUroJMV7YQ7p+8O 7FLdoyuHNGGNA== Received: by phobos.denx.de (Postfix, from userid 109) id 3088384BCE; Thu, 22 Sep 2022 07:18:41 +0200 (CEST) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [IPv6:2001:67c:2050:101:465::204]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3750F84CA3 for ; Thu, 22 Sep 2022 07:18:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:b231:465::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4MY3Tm21W3z9sW9; Thu, 22 Sep 2022 07:18:36 +0200 (CEST) Message-ID: Date: Thu, 22 Sep 2022 07:18:34 +0200 MIME-Version: 1.0 Subject: Re: [PATCH v4 2/5] usb: ehci: ehci-marvell: Support for marvell,ac5-ehci Content-Language: en-US To: Chris Packham Cc: Elad Nachman , Vadym Kochan , Adam Ford , Lukasz Majewski , =?UTF-8?Q?Marek_Beh=c3=ban?= , Marek Vasut , =?UTF-8?Q?Pali_Roh=c3=a1r?= , Weijie Gao , u-boot@lists.denx.de References: <20220922033116.915635-1-judge.packham@gmail.com> <20220922033116.915635-3-judge.packham@gmail.com> From: Stefan Roese In-Reply-To: <20220922033116.915635-3-judge.packham@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Rspamd-Queue-Id: 4MY3Tm21W3z9sW9 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 22.09.22 05:31, Chris Packham wrote: > Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci > block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with > the fact that the ac5 does not have the mbus infrastructure the 32-bit > SoCs have and ensure USB_EHCI_IS_TDI is selected. > > Signed-off-by: Chris Packham > --- > > (no changes since v1) > > drivers/usb/host/Kconfig | 1 + > drivers/usb/host/ehci-marvell.c | 57 +++++++++++++++++++++++++++------ > 2 files changed, 48 insertions(+), 10 deletions(-) > > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig > index a0f48f09a7..628078f495 100644 > --- a/drivers/usb/host/Kconfig > +++ b/drivers/usb/host/Kconfig > @@ -178,6 +178,7 @@ config USB_EHCI_MARVELL > depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X > default y > select USB_EHCI_IS_TDI if !ARM64 > + select USB_EHCI_IS_TDI if ALLEYCAT_5 > ---help--- > Enables support for the on-chip EHCI controller on MVEBU SoCs. > > diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c > index b7e60c690a..7d859b9cce 100644 > --- a/drivers/usb/host/ehci-marvell.c > +++ b/drivers/usb/host/ehci-marvell.c > @@ -48,12 +48,17 @@ struct ehci_mvebu_priv { > fdt_addr_t hcd_base; > }; > > +#define USB_TO_DRAM_TARGET_ID 0x2 > +#define USB_TO_DRAM_ATTR_ID 0x0 > +#define USB_DRAM_BASE 0x00000000 > +#define USB_DRAM_SIZE 0xfff /* don't overrun u-boot source (was 0xffff) */ > + > /* > * Once all the older Marvell SoC's (Orion, Kirkwood) are converted > * to the common mvebu archticture including the mbus setup, this > * will be the only function needed to configure the access windows > */ > -static void usb_brg_adrdec_setup(void *base) > +static void usb_brg_adrdec_setup(struct udevice *dev, void *base) > { > const struct mbus_dram_target_info *dram; > int i; > @@ -65,16 +70,34 @@ static void usb_brg_adrdec_setup(void *base) > writel(0, base + USB_WINDOW_BASE(i)); > } > > - for (i = 0; i < dram->num_cs; i++) { > - const struct mbus_dram_window *cs = dram->cs + i; > + if (device_is_compatible(dev, "marvell,ac5-ehci")) { > + /* > + * use decoding window to map dram address seen by usb to 0x0 > + */ > > /* Write size, attributes and target id to control register */ > - writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | > - (dram->mbus_dram_target_id << 4) | 1, > - base + USB_WINDOW_CTRL(i)); > + writel((USB_DRAM_SIZE << 16) | (USB_TO_DRAM_ATTR_ID << 8) | > + (USB_TO_DRAM_TARGET_ID << 4) | 1, > + base + USB_WINDOW_CTRL(0)); Nitpicking / coding-style comment: Not aligned with the '(' in the line above. I assume that checkpatch.pl will complain here. > > /* Write base address to base register */ > - writel(cs->base, base + USB_WINDOW_BASE(i)); > + writel(USB_DRAM_BASE, base + USB_WINDOW_BASE(0)); > + > + debug("## AC5 decoding windows, ctrl[%p]=0x%x, base[%p]=0x%x\n", > + base + USB_WINDOW_CTRL(0), readl(base + USB_WINDOW_CTRL(0)), > + base + USB_WINDOW_BASE(0), readl(base + USB_WINDOW_BASE(0))); > + } else { > + for (i = 0; i < dram->num_cs; i++) { > + const struct mbus_dram_window *cs = dram->cs + i; > + > + /* Write size, attributes and target id to control register */ > + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | > + (dram->mbus_dram_target_id << 4) | 1, > + base + USB_WINDOW_CTRL(i)); > + > + /* Write base address to base register */ > + writel(cs->base, base + USB_WINDOW_BASE(i)); > + } > } > } > > @@ -126,15 +149,28 @@ static int ehci_mvebu_probe(struct udevice *dev) > if (device_is_compatible(dev, "marvell,armada-3700-ehci")) > marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup; > else > - usb_brg_adrdec_setup((void *)priv->hcd_base); > + usb_brg_adrdec_setup(dev, (void *)priv->hcd_base); > > hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100); > hcor = (struct ehci_hcor *) > ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); > > debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n", > - (uintptr_t)hccr, (uintptr_t)hcor, > - (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); > + (uintptr_t)hccr, (uintptr_t)hcor, > + (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); Unrelated change of indentation (see above). > + > +#define PHY_CALIB_OFFSET 0x808 > + /* > + * Trigger calibration during each usb start/reset: > + * BIT 13 to 0, and then to 1 > + */ > + if (device_is_compatible(dev, "marvell,ac5-ehci")) { > + void *phy_calib_reg = (void *)(priv->hcd_base + PHY_CALIB_OFFSET); > + u32 val = readl(phy_calib_reg) & (~BIT(13)); > + > + writel(val, phy_calib_reg); > + writel(val | BIT(13), phy_calib_reg); > + } > > return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0, > USB_INIT_HOST); > @@ -143,6 +179,7 @@ static int ehci_mvebu_probe(struct udevice *dev) > static const struct udevice_id ehci_usb_ids[] = { > { .compatible = "marvell,orion-ehci", }, > { .compatible = "marvell,armada-3700-ehci", }, > + { .compatible = "marvell,ac5-ehci", }, > { } > }; > Other than this: Reviewed-by: Stefan Roese Thanks, Stefan