From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZhO3-000398-9W for qemu-devel@nongnu.org; Wed, 19 Dec 2018 14:20:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZhNy-0002Ch-VB for qemu-devel@nongnu.org; Wed, 19 Dec 2018 14:20:07 -0500 From: Alistair Francis Date: Wed, 19 Dec 2018 19:19:59 +0000 Message-ID: References: In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: [Qemu-devel] [PATCH v2 21/23] tcg: Add RISC-V cpu signal handler List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" Cc: Alistair Francis , "alistair23@gmail.com" , "richard.henderson@linaro.org" Signed-off-by: Alistair Francis Signed-off-by: Michael Clark --- accel/tcg/user-exec.c | 75 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cd75829cf2..941295ea49 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -571,6 +571,81 @@ int cpu_signal_handler(int host_signum, void *pinfo, return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } =20 +#elif defined(__riscv) + +int cpu_signal_handler(int host_signum, void *pinfo, + void *puc) +{ + siginfo_t *info =3D pinfo; + ucontext_t *uc =3D puc; + greg_t pc =3D uc->uc_mcontext.__gregs[REG_PC]; + uint32_t insn =3D *(uint32_t *)pc; + int is_write =3D 0; + + /* Detect store by reading the instruction at the program + counter. Note: we currently only generate 32-bit + instructions so we thus only detect 32-bit stores */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + is_write =3D 1; + break; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + is_write =3D 1; + break; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + is_write =3D 1; + break; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + is_write =3D 1; + break; + default: + break; + } + break; + default: + break; + } + + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); +} + #else =20 #error host CPU specific signal handler needed --=20 2.19.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1gZhOP-0003T6-JQ for mharc-qemu-riscv@gnu.org; Wed, 19 Dec 2018 14:20:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46375) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gZhOJ-0003Mz-Vr for qemu-riscv@nongnu.org; Wed, 19 Dec 2018 14:20:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gZhOA-0002QE-KH for qemu-riscv@nongnu.org; Wed, 19 Dec 2018 14:20:21 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:16010) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gZhNy-0002BP-LT; Wed, 19 Dec 2018 14:20:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1545247202; x=1576783202; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; 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X-Received-From: 216.71.153.141 Subject: [Qemu-riscv] [PATCH v2 21/23] tcg: Add RISC-V cpu signal handler X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Dec 2018 19:20:28 -0000 Signed-off-by: Alistair Francis Signed-off-by: Michael Clark --- accel/tcg/user-exec.c | 75 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cd75829cf2..941295ea49 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -571,6 +571,81 @@ int cpu_signal_handler(int host_signum, void *pinfo, return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } =20 +#elif defined(__riscv) + +int cpu_signal_handler(int host_signum, void *pinfo, + void *puc) +{ + siginfo_t *info =3D pinfo; + ucontext_t *uc =3D puc; + greg_t pc =3D uc->uc_mcontext.__gregs[REG_PC]; + uint32_t insn =3D *(uint32_t *)pc; + int is_write =3D 0; + + /* Detect store by reading the instruction at the program + counter. Note: we currently only generate 32-bit + instructions so we thus only detect 32-bit stores */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + is_write =3D 1; + break; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + is_write =3D 1; + break; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + is_write =3D 1; + break; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + is_write =3D 1; + break; + default: + break; + } + break; + default: + break; + } + + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); +} + #else =20 #error host CPU specific signal handler needed --=20 2.19.1