From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2951C433EF for ; Sat, 23 Oct 2021 18:19:43 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D02B860F5D for ; Sat, 23 Oct 2021 18:19:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D02B860F5D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=aosc.io Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B0F5583173; Sat, 23 Oct 2021 20:19:40 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aosc.io Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=mymailcheap.com header.i=@mymailcheap.com header.b="xJNMkHv2"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=aosc.io header.i=@aosc.io header.b="N2d9Ok3m"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id E0626831B2; Sat, 23 Oct 2021 20:19:38 +0200 (CEST) Received: from relay4.mymailcheap.com (relay4.mymailcheap.com [137.74.80.154]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E4A068314C for ; Sat, 23 Oct 2021 20:19:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aosc.io Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=icenowy@aosc.io Received: from filter2.mymailcheap.com (filter2.mymailcheap.com [91.134.140.82]) by relay4.mymailcheap.com (Postfix) with ESMTPS id 7D2D22004C; Sat, 23 Oct 2021 18:19:34 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by filter2.mymailcheap.com (Postfix) with ESMTP id 5B9892A90A; Sat, 23 Oct 2021 20:19:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mymailcheap.com; s=default; t=1635013174; bh=cGj8BMIqhe3IRtIKNUGNlKUczkThx55MCo4L0PdX144=; h=Subject:From:To:Date:In-Reply-To:References:From; b=xJNMkHv2v9zr5ncYfSlrSUdoVeIZcF6Qi9g4TAjmUd3o+2tkL4bcsWjSyCjnH+pkW neQ6IIDftTwgn65xo2KJFlPp+Dbo1PrHXRE5eSENpF8CaMGD9mqHEgQZL+x+eJDEBX dICl/tQ58SCyywG7BxWrHDUN4kc2uoEgUJVddaJw= Received: from filter2.mymailcheap.com ([127.0.0.1]) by localhost (filter2.mymailcheap.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5U-VjcpUncjr; Sat, 23 Oct 2021 20:19:33 +0200 (CEST) Received: from mail20.mymailcheap.com (mail20.mymailcheap.com [51.83.111.147]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by filter2.mymailcheap.com (Postfix) with ESMTPS; Sat, 23 Oct 2021 20:19:33 +0200 (CEST) Received: from ice-e5v2.lan (unknown [59.41.160.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 21A2C400B3; Sat, 23 Oct 2021 18:19:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=aosc.io; s=default; t=1635013172; bh=cGj8BMIqhe3IRtIKNUGNlKUczkThx55MCo4L0PdX144=; h=Subject:From:To:Date:In-Reply-To:References:From; b=N2d9Ok3mMoBXIN83l/J16iItD60c0eNpkO3wWDnaAwb/9SgWLICbKWDEv3jPt56bI eRCymPWv81yqjgDrHej0Joz8teQea3xJZMO+ZL1rIf29RzEc8WrHNjMmxDrD3owEoV rKv1A4opDT6QGIvtixE5O+P7UeNansnTNGsig74k= Message-ID: Subject: Re: [PATCH] phy: rockchip: inno-usb2: fix hang when multiple controllers exit From: Icenowy Zheng To: Siva Mahadevan , u-boot@lists.denx.de Date: Sun, 24 Oct 2021 02:19:24 +0800 In-Reply-To: References: <20210406151059.1187379-1-icenowy@aosc.io> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean 在 2021-10-23星期六的 13:23 -0400，Siva Mahadevan写道： > Icenowy Zheng wrote: > > The OHCI and EHCI controllers are both bound to the same PHY. They > > will > > both do init and power_on operations when the controller is brought > > up > > and both do power_off and exit when the controller is stopped. > > However, > > the PHY uclass of U-Boot is not as sane as we thought -- they won't > > maintain a status mark for PHYs, and thus the functions of the PHYs > > could be called for multiple times. Calling init/power_on for > > multiple > > times have no severe problems, however calling power_off/exit for > > multiple times have a problem -- the first exit call will stop the > > PHY > > clock, and power_off/exit calls after it still trying to write to > > PHY > > registers. The write operation to PHY registers will fail because > > clock > > is already stopped. > > > > Adapt the count mechanism from phy-sun4i-usb to both init/exit and > > power_on/power_off functions to phy-rockchip-inno-usb2 to fix this > > problem. With this stopping USB controllers (manually or before > > booting > > a kernel) will work. > > > > Signed-off-by: Icenowy Zheng > > Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver") > > --- > >  drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 21 > > +++++++++++++++++++ > >  1 file changed, 21 insertions(+) > > > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > > b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > > index 62b8ba3a4a..be9cc99d90 100644 > > --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > > +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c > > @@ -62,6 +62,8 @@ struct rockchip_usb2phy { > >         void *reg_base; > >         struct clk phyclk; > >         const struct rockchip_usb2phy_cfg *phy_cfg; > > +       int init_count; > > +       int power_on_count; > >  }; > >   > >  static inline int property_enable(void *reg_base, > > @@ -92,6 +94,10 @@ static int rockchip_usb2phy_power_on(struct phy > > *phy) > >         struct rockchip_usb2phy *priv = dev_get_priv(parent); > >         const struct rockchip_usb2phy_port_cfg *port_cfg = > > us2phy_get_port(phy); > >   > > +       priv->power_on_count++; > > +       if (priv->power_on_count != 1) > > +               return 0; > > + > >         property_enable(priv->reg_base, &port_cfg->phy_sus, false); > >   > >         /* waiting for the utmi_clk to become stable */ > > @@ -106,6 +112,10 @@ static int rockchip_usb2phy_power_off(struct > > phy *phy) > >         struct rockchip_usb2phy *priv = dev_get_priv(parent); > >         const struct rockchip_usb2phy_port_cfg *port_cfg = > > us2phy_get_port(phy); > >   > > +       priv->power_on_count--; > > +       if (priv->power_on_count != 0) > > +               return 0; > > + > >         property_enable(priv->reg_base, &port_cfg->phy_sus, true); > >   > >         return 0; > > @@ -118,6 +128,10 @@ static int rockchip_usb2phy_init(struct phy > > *phy) > >         const struct rockchip_usb2phy_port_cfg *port_cfg = > > us2phy_get_port(phy); > >         int ret; > >   > > +       priv->init_count++; > > +       if (priv->init_count != 1) > > +               return 0; > > + > >         ret = clk_enable(&priv->phyclk); > >         if (ret) { > >                 dev_err(phy->dev, "failed to enable phyclk > > (ret=%d)\n", ret); > > @@ -140,6 +154,10 @@ static int rockchip_usb2phy_exit(struct phy > > *phy) > >         struct udevice *parent = dev_get_parent(phy->dev); > >         struct rockchip_usb2phy *priv = dev_get_priv(parent); > >   > > +       priv->init_count--; > > +       if (priv->init_count != 0) > > +               return 0; > > + > >         clk_disable(&priv->phyclk); > >   > >         return 0; > > @@ -212,6 +230,9 @@ static int rockchip_usb2phy_probe(struct > > udevice *dev) > >                 return ret; > >         } > >   > > +       priv->power_on_count = 0; > > +       priv->init_count = 0; > > + > >         return 0; > >  } > >   > > -- > > 2.30.2 > > Are there any plans of submitting this patch to u-boot mainline? I > recently got a pinebook pro and got u-boot mainline working as-is > plus > this patch. I can confirm that this fixes the issue for me. The current maintainer wants a fix in PHY framework instead of the specific driver, but I am recently not interested in fixing it (because PBP is my daily driver now, and I don't dare to do dangerous BL development that will lead to regression on it).