From mboxrd@z Thu Jan  1 00:00:00 1970
From: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Date: Tue, 8 Dec 2020 18:25:13 +0100
Subject: [PATCH 2/4] ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock
In-Reply-To: <ca080b136e214a3285da43b8fb044170@SFHDAG2NODE3.st.com>
References: <20201201102920.84051-1-marex@denx.de>
 <20201201102920.84051-2-marex@denx.de>
 <ca080b136e214a3285da43b8fb044170@SFHDAG2NODE3.st.com>
Message-ID: <c49134c3-2235-9429-dd4c-34dab85ce877@foss.st.com>
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To: u-boot@lists.denx.de

Hi Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: mardi 1 d?cembre 2020 11:29
>
> The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter or without one on the SDMMC1 interface. Because the SDMMC1 interface is limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback clock to permit operation of the same U-Boot image on both SoM with and without voltage level shifter.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrice Chotard <patrice.chotard@st.com>
> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> ---
>   arch/arm/dts/stm32mp15xx-dhcom.dtsi | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> index 9049245c5b..dafcce4323 100644
> --- a/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> +++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
> @@ -333,7 +333,6 @@
>   	disable-wp;
>   	st,sig-dir;
>   	st,neg-edge;
> -	st,use-ckin;
>   	bus-width = <4>;
>   	vmmc-supply = <&vdd_sd>;
>   	status = "okay";
> --
> 2.29.2
>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Thanks

Patrick