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From: "Souza, Jose" <jose.souza@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "mika.kuoppala@linux.intel.com" <mika.kuoppala@linux.intel.com>,
	"Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Only access SFC_DONE when media domain is not fused off
Date: Wed, 11 Aug 2021 20:55:48 +0000	[thread overview]
Message-ID: <c53a507f96eadee5178062305c999ff1250999c9.camel@intel.com> (raw)
In-Reply-To: <20210806174130.1058960-1-matthew.d.roper@intel.com>

On Fri, 2021-08-06 at 10:41 -0700, Matt Roper wrote:
> The SFC_DONE register lives within the corresponding VD0/VD2/VD4/VD6
> forcewake domain and is not accessible if the vdbox in that domain is
> fused off and the forcewake is not initialized.
> 
> This mistake went unnoticed because until recently we were using the
> wrong register offset for the SFC_DONE register; once the register
> offset was corrected, we started hitting errors like
> 
>   <4> [544.989065] i915 0000:cc:00.0: Uninitialized forcewake domain(s) 0x80 accessed at 0x1ce000
> 
> on parts with fused-off vdbox engines.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Fixes: e50dbdbfd9fb ("drm/i915/tgl: Add SFC instdone to error state")
> Fixes: 82929a2140eb ("drm/i915: Correct SFC_DONE register offset")
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 0f08bcfbe964..9cf6ac575de1 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -727,9 +727,18 @@ static void err_print_gt(struct drm_i915_error_state_buf *m,
>  	if (GRAPHICS_VER(m->i915) >= 12) {
>  		int i;
>  
> -		for (i = 0; i < GEN12_SFC_DONE_MAX; i++)
> +		for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
> +			/*
> +			 * SFC_DONE resides in the VD forcewake domain, so it
> +			 * only exists if the corresponding VCS engine is
> +			 * present.
> +			 */
> +			if (!HAS_ENGINE(gt->_gt, _VCS(i * 2)))
> +				continue;
> +
>  			err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
>  				   gt->sfc_done[i]);
> +		}
>  
>  		err_printf(m, "  GAM_DONE: 0x%08x\n", gt->gam_done);
>  	}
> @@ -1598,6 +1607,14 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
>  
>  	if (GRAPHICS_VER(i915) >= 12) {
>  		for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
> +			/*
> +			 * SFC_DONE resides in the VD forcewake domain, so it
> +			 * only exists if the corresponding VCS engine is
> +			 * present.
> +			 */
> +			if (!HAS_ENGINE(gt->_gt, _VCS(i * 2)))
> +				continue;
> +
>  			gt->sfc_done[i] =
>  				intel_uncore_read(uncore, GEN12_SFC_DONE(i));
>  		}


  parent reply	other threads:[~2021-08-11 20:55 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-06 17:41 [Intel-gfx] [PATCH] drm/i915: Only access SFC_DONE when media domain is not fused off Matt Roper
2021-08-06 18:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-08-06 19:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-08-07  0:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-11 20:55 ` Souza, Jose [this message]
2021-08-11 21:04   ` [Intel-gfx] [PATCH] " Matt Roper

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