From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68946C4332F for ; Wed, 2 Nov 2022 19:06:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231742AbiKBTGG (ORCPT ); Wed, 2 Nov 2022 15:06:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231445AbiKBTGD (ORCPT ); Wed, 2 Nov 2022 15:06:03 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 927A92D4; Wed, 2 Nov 2022 12:06:01 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A2J5TAb077081; Wed, 2 Nov 2022 14:05:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667415929; bh=mzZxMJVEQJpXDhPObxYGdoDYN7/gCqvCB8snGGAKPqw=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=ud4Dk8CNutSABAEQ8bFYxzZUYQMXzbgLf+Tgt8LFI1Lr+7fYPpXCTzBchXH1fixL/ 91oxTNbVg//JFqaLWf/j5vWzyb8vXGIn/Ejar8qqbY6j7kKMkUlx3VeSTGv7ubaScU t45aWlDphfeVnhZqLSQK82OGKVkLGuHYuJoroVg8= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A2J5TbQ018384 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Nov 2022 14:05:29 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 2 Nov 2022 14:05:29 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 2 Nov 2022 14:05:29 -0500 Received: from [10.249.33.217] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A2J5SAm110083; Wed, 2 Nov 2022 14:05:28 -0500 Message-ID: Date: Wed, 2 Nov 2022 14:05:28 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v4 1/9] dt-bindings: mfd: Add TI-Nspire misc registers Content-Language: en-US To: Rob Herring CC: Lee Jones , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt , , , References: <20221101215804.16262-1-afd@ti.com> <20221101215804.16262-2-afd@ti.com> <20221102173558.GA4193055-robh@kernel.org> From: Andrew Davis In-Reply-To: <20221102173558.GA4193055-robh@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/2/22 12:35 PM, Rob Herring wrote: > On Tue, Nov 01, 2022 at 04:57:56PM -0500, Andrew Davis wrote: >> The TI Nspire devices contain a set of registers with a seemingly >> miscellaneous set of functionality. This area is known simply as the >> "misc" region. >> >> Signed-off-by: Andrew Davis >> --- >> .../bindings/mfd/ti,nspire-misc.yaml | 55 +++++++++++++++++++ >> 1 file changed, 55 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml >> >> diff --git a/Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml b/Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml >> new file mode 100644 >> index 0000000000000..d409eae7537bd >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml >> @@ -0,0 +1,55 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mfd/ti,nspire-misc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: TI Nspire MISC hardware block >> + >> +maintainers: >> + - Andrew Davis >> + >> +description: | >> + System controller node represents a register region containing a set >> + of miscellaneous registers. The registers are not cohesive enough to >> + represent as any specific type of device. The typical use-case is >> + for some other node's driver, or platform-specific code, to acquire >> + a reference to the syscon node (e.g. by phandle, node path, or >> + search using a specific compatible value), interrogate the node (or >> + associated OS driver) to determine the location of the registers, >> + and access the registers directly. > > Looks like you copied the generic description? Describe what MISC > contains. > I don't know what all MISC contains (or maybe I do, but it is not publicly available so I'm not going to add anything that hasn't already been found by clean-room reverse engineering [0]). This is the point I was trying to make in that thread on v3. The node's content *is* the hardware description. Every time a new register is found it could have just been added to the DT. But now we also have to go back here and add the exact same information to the binding, every time. We don't require that for simple-bus, should simple-mfd be given the same flexibility? [0] https://hackspire.org/index.php?title=Memory-mapped_I/O_ports_on_Classic#900A0000_-_Miscellaneous >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - ti,nspire-misc >> + - const: syscon >> + - const: simple-mfd >> + >> + reg: >> + maxItems: 1 >> + >> + reboot: >> + $ref: "../power/reset/syscon-reboot.yaml" > > /schemas/power/... > > And no quotes needed. > Will fix. Andrew >> + >> +required: >> + - compatible >> + - reg >> + - reboot >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + misc: misc@900a0000 { >> + compatible = "ti,nspire-misc", "syscon", "simple-mfd"; >> + reg = <0x900a0000 0x1000>; >> + >> + reboot { >> + compatible = "syscon-reboot"; >> + offset = <0x08>; >> + value = <0x02>; >> + }; >> + }; >> -- >> 2.37.3 >> >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8196BC4332F for ; Wed, 2 Nov 2022 19:07:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=b2R92CmsPJt+xZ9FfCv7rL0EBSdCJgXqjYQz3Ognlss=; b=d0gc9PJGZtkTjX 06Q1pjH8e3P6hIauKyxJfjFWSF06XEG2BJ6QPY/SJjNmBc0MRdum7xOd0fsoJz+qgYgiNGEHnIy28 xijUK9SfniJlyDYr7C/3zz/OdN88/mtdLAp5kj3J9R1RqdrR5RiReEXHe56q2IcYBc/twiUHTw9kA zr8IpQ5eQGHgmp6pupVgIkvpTKVhiNmk4aeANpRUIcTD+fBeYBJlal9CuyKE1hQlb6cWltnldfWal cBZLL5Bn3WJGMZG/kMSv41bG/XJejGHo0n/bqjHCRMq2Sh0jfCJjsWQaetCIN8QuQDYPSZN3nayvj 36TtOY44SCaDU/p/y0OA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqJ3n-00DS9e-P9; Wed, 02 Nov 2022 19:05:59 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oqJ3k-00DS3C-GP for linux-arm-kernel@lists.infradead.org; Wed, 02 Nov 2022 19:05:58 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A2J5TAb077081; Wed, 2 Nov 2022 14:05:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667415929; bh=mzZxMJVEQJpXDhPObxYGdoDYN7/gCqvCB8snGGAKPqw=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=ud4Dk8CNutSABAEQ8bFYxzZUYQMXzbgLf+Tgt8LFI1Lr+7fYPpXCTzBchXH1fixL/ 91oxTNbVg//JFqaLWf/j5vWzyb8vXGIn/Ejar8qqbY6j7kKMkUlx3VeSTGv7ubaScU t45aWlDphfeVnhZqLSQK82OGKVkLGuHYuJoroVg8= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A2J5TbQ018384 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Nov 2022 14:05:29 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Wed, 2 Nov 2022 14:05:29 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Wed, 2 Nov 2022 14:05:29 -0500 Received: from [10.249.33.217] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A2J5SAm110083; Wed, 2 Nov 2022 14:05:28 -0500 Message-ID: Date: Wed, 2 Nov 2022 14:05:28 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v4 1/9] dt-bindings: mfd: Add TI-Nspire misc registers Content-Language: en-US To: Rob Herring CC: Lee Jones , Krzysztof Kozlowski , Arnd Bergmann , Linus Walleij , Geert Uytterhoeven , Daniel Tang , Fabian Vogt , , , References: <20221101215804.16262-1-afd@ti.com> <20221101215804.16262-2-afd@ti.com> <20221102173558.GA4193055-robh@kernel.org> From: Andrew Davis In-Reply-To: <20221102173558.GA4193055-robh@kernel.org> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221102_120556_730655_0F9C369C X-CRM114-Status: GOOD ( 26.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/2/22 12:35 PM, Rob Herring wrote: > On Tue, Nov 01, 2022 at 04:57:56PM -0500, Andrew Davis wrote: >> The TI Nspire devices contain a set of registers with a seemingly >> miscellaneous set of functionality. This area is known simply as the >> "misc" region. >> >> Signed-off-by: Andrew Davis >> --- >> .../bindings/mfd/ti,nspire-misc.yaml | 55 +++++++++++++++++++ >> 1 file changed, 55 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml >> >> diff --git a/Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml b/Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml >> new file mode 100644 >> index 0000000000000..d409eae7537bd >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml >> @@ -0,0 +1,55 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mfd/ti,nspire-misc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: TI Nspire MISC hardware block >> + >> +maintainers: >> + - Andrew Davis >> + >> +description: | >> + System controller node represents a register region containing a set >> + of miscellaneous registers. The registers are not cohesive enough to >> + represent as any specific type of device. The typical use-case is >> + for some other node's driver, or platform-specific code, to acquire >> + a reference to the syscon node (e.g. by phandle, node path, or >> + search using a specific compatible value), interrogate the node (or >> + associated OS driver) to determine the location of the registers, >> + and access the registers directly. > > Looks like you copied the generic description? Describe what MISC > contains. > I don't know what all MISC contains (or maybe I do, but it is not publicly available so I'm not going to add anything that hasn't already been found by clean-room reverse engineering [0]). This is the point I was trying to make in that thread on v3. The node's content *is* the hardware description. Every time a new register is found it could have just been added to the DT. But now we also have to go back here and add the exact same information to the binding, every time. We don't require that for simple-bus, should simple-mfd be given the same flexibility? [0] https://hackspire.org/index.php?title=Memory-mapped_I/O_ports_on_Classic#900A0000_-_Miscellaneous >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - ti,nspire-misc >> + - const: syscon >> + - const: simple-mfd >> + >> + reg: >> + maxItems: 1 >> + >> + reboot: >> + $ref: "../power/reset/syscon-reboot.yaml" > > /schemas/power/... > > And no quotes needed. > Will fix. Andrew >> + >> +required: >> + - compatible >> + - reg >> + - reboot >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + misc: misc@900a0000 { >> + compatible = "ti,nspire-misc", "syscon", "simple-mfd"; >> + reg = <0x900a0000 0x1000>; >> + >> + reboot { >> + compatible = "syscon-reboot"; >> + offset = <0x08>; >> + value = <0x02>; >> + }; >> + }; >> -- >> 2.37.3 >> >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel