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([2a01:c22:b04f:b200:7a70:bbc8:8101:45be]) by smtp.gmail.com with ESMTPSA id 79sm15159984wmb.7.2019.09.29.07.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Sep 2019 07:39:24 -0700 (PDT) Message-ID: Subject: Re: [PATCH 08/14] hw/arm/bcm2836: Make the SoC code modular From: Esteban Bosse To: Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= , Peter Maydell , Andrew Baumann , qemu-devel@nongnu.org, Pekka Enberg , =?ISO-8859-1?Q?Zolt=E1n?= Baldaszti Date: Sun, 29 Sep 2019 16:39:14 +0200 In-Reply-To: <20190904171315.8354-9-f4bug@amsat.org> References: <20190904171315.8354-1-f4bug@amsat.org> <20190904171315.8354-9-f4bug@amsat.org> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5-1.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, Clement Deschamps , =?ISO-8859-1?Q?Marc-Andr=E9?= Lureau , Paolo Bonzini , Philippe =?ISO-8859-1?Q?Mathieu-Daud=E9?= , Luc Michel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" El mié, 04-09-2019 a las 19:13 +0200, Philippe Mathieu-Daudé escribió: > This file creates the BCM2836/BCM2837 blocks. > The biggest differences with the BCM2838 we are going to add, are > the base addresses of the interrupt controller and the peripherals. > Add these addresses in the BCM283XInfo structure to make this > block more modular. Remove the MCORE_OFFSET offset as it is > not useful and rather confusing. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/arm/bcm2836.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c > index 493a913f89..019e67b906 100644 > --- a/hw/arm/bcm2836.c > +++ b/hw/arm/bcm2836.c > @@ -16,15 +16,11 @@ > #include "hw/arm/raspi_platform.h" > #include "hw/sysbus.h" > > -/* Peripheral base address seen by the CPU */ > -#define BCM2836_PERI_BASE 0x3F000000 > - > -/* "QA7" (Pi2) interrupt controller and mailboxes etc. */ > -#define BCM2836_CONTROL_BASE 0x40000000 > - > struct BCM283XInfo { > const char *name; > const char *cpu_type; > + hwaddr peri_base; /* Peripheral base address seen by the CPU */ > + hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ > int clusterid; > }; > > @@ -32,12 +28,16 @@ static const BCM283XInfo bcm283x_socs[] = { > { > .name = TYPE_BCM2836, > .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"), > + .peri_base = 0x3f000000, > + .ctrl_base = 0x40000000, > .clusterid = 0xf, > }, > #ifdef TARGET_AARCH64 > { > .name = TYPE_BCM2837, > .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), > + .peri_base = 0x3f000000, > + .ctrl_base = 0x40000000, > .clusterid = 0x0, > }, > #endif > @@ -104,7 +104,7 @@ static void bcm2836_realize(DeviceState *dev, > Error **errp) > } > > sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, > - BCM2836_PERI_BASE, 1); > + info->peri_base, 1); > > /* bcm2836 interrupt controller (and mailboxes, etc.) */ > object_property_set_bool(OBJECT(&s->control), true, "realized", > &err); > @@ -113,7 +113,7 @@ static void bcm2836_realize(DeviceState *dev, > Error **errp) > return; > } > > - sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, > BCM2836_CONTROL_BASE); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info- > >ctrl_base); > > sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, > qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); > @@ -126,7 +126,7 @@ static void bcm2836_realize(DeviceState *dev, > Error **errp) > > /* set periphbase/CBAR value for CPU-local registers */ > object_property_set_int(OBJECT(&s->cpus[n]), > - BCM2836_PERI_BASE + MCORE_OFFSET, > + info->peri_base, > "reset-cbar", &err); > if (err) { > error_propagate(errp, err); Reviewed-by: Esteban Bosse