[PATCH 0/3] x86/svm: virtual VMLOAD/VMSAVE

[PATCH 0/3] x86/svm: virtual VMLOAD/VMSAVE

[brian.woods]

From: Brian Woods <brian.woods@amd.com>

x86/svm: virtual VMLOAD/VMSAVE

On AMD family 17h server processors, there is a feature called virtual
VMLOAD/VMSAVE.  This allows a nested hypervisor to preform a VMLOAD or
VMSAVE without needing to be intercepted by the host hypervisor.
Virtual VMLOAD/VMSAVE requires the host hypervisor to be in long mode
and nested page tables to be enabled.  For more information about it
please see:

AMD64 Architecture Programmer’s Manual Volume 2: System Programming
http://support.amd.com/TechDocs/24593.pdf
Section: VMSAVE and VMLOAD Virtualization (Section 15.33.1)

This patch series adds support to check for and enable the virtual
VMLOAD/VMSAVE features if available.

Signed-off-by: Brian Woods <brian.woods@amd.com>

Brian Woods (3):
  x86/svm: rename lbr control field in vmcb
  x86/svm: add virtual VMLOAD/VMSAVE feature definition
  x86/svm: add virtual VMLOAD/VMSAVE support

 xen/arch/x86/hvm/svm/nestedsvm.c        | 10 +++++-----
 xen/arch/x86/hvm/svm/svm.c              |  3 ++-
 xen/arch/x86/hvm/svm/svmdebug.c         |  2 ++
 xen/arch/x86/hvm/svm/vmcb.c             |  7 +++++++
 xen/include/asm-x86/hvm/svm/nestedsvm.h |  4 ++--
 xen/include/asm-x86/hvm/svm/svm.h       |  2 ++
 xen/include/asm-x86/hvm/svm/vmcb.h      |  7 ++++---
 7 files changed, 24 insertions(+), 11 deletions(-)

-- 
2.11.0


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[PATCH 1/3] x86/svm: rename lbr control field in vmcb

[brian.woods]

From: Brian Woods <brian.woods@amd.com>

Rename the lbr_control field in the vmcb for future/upcoming changes.

Signed-off-by: Brian Woods <brian.woods@amd.com>
---
 xen/arch/x86/hvm/svm/nestedsvm.c        | 10 +++++-----
 xen/arch/x86/hvm/svm/svm.c              |  2 +-
 xen/include/asm-x86/hvm/svm/nestedsvm.h |  4 ++--
 xen/include/asm-x86/hvm/svm/vmcb.h      |  6 +++---
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nestedsvm.c
index 1de896e456..5513f7a388 100644
--- a/xen/arch/x86/hvm/svm/nestedsvm.c
+++ b/xen/arch/x86/hvm/svm/nestedsvm.c
@@ -174,7 +174,7 @@ int nsvm_vcpu_reset(struct vcpu *v)
     svm->ns_exception_intercepts = 0;
     svm->ns_general1_intercepts = 0;
     svm->ns_general2_intercepts = 0;
-    svm->ns_lbr_control.bytes = 0;
+    svm->ns_virt_ext.bytes = 0;
 
     svm->ns_hap_enabled = 0;
     svm->ns_vmcb_guestcr3 = 0;
@@ -521,12 +521,12 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, struct cpu_user_regs *regs)
     /* Pending Interrupts */
     n2vmcb->eventinj = ns_vmcb->eventinj;
 
-    /* LBR virtualization */
+    /* LBR and other virtualization */
     if (!vcleanbit_set(lbr)) {
-        svm->ns_lbr_control = ns_vmcb->lbr_control;
+        svm->ns_virt_ext = ns_vmcb->virt_ext;
     }
-    n2vmcb->lbr_control.bytes =
-        n1vmcb->lbr_control.bytes | ns_vmcb->lbr_control.bytes;
+    n2vmcb->virt_ext.bytes =
+        n1vmcb->virt_ext.bytes | ns_vmcb->virt_ext.bytes;
 
     /* NextRIP - only evaluated on #VMEXIT. */
 
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index b9cf423fd9..c8ffb17515 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1997,7 +1997,7 @@ static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content)
         vmcb_set_debugctlmsr(vmcb, msr_content);
         if ( !msr_content || !cpu_has_svm_lbrv )
             break;
-        vmcb->lbr_control.fields.enable = 1;
+        vmcb->virt_ext.fields.lbr_enable = 1;
         svm_disable_intercept_for_msr(v, MSR_IA32_DEBUGCTLMSR);
         svm_disable_intercept_for_msr(v, MSR_IA32_LASTBRANCHFROMIP);
         svm_disable_intercept_for_msr(v, MSR_IA32_LASTBRANCHTOIP);
diff --git a/xen/include/asm-x86/hvm/svm/nestedsvm.h b/xen/include/asm-x86/hvm/svm/nestedsvm.h
index 4b36c25c5d..a619b6131b 100644
--- a/xen/include/asm-x86/hvm/svm/nestedsvm.h
+++ b/xen/include/asm-x86/hvm/svm/nestedsvm.h
@@ -46,8 +46,8 @@ struct nestedsvm {
     uint32_t ns_general1_intercepts;
     uint32_t ns_general2_intercepts;
 
-    /* Cached real lbr of the l2 guest */
-    lbrctrl_t ns_lbr_control;
+    /* Cached real lbr and other virtual extentions of the l2 guest */
+    virt_ext_t ns_virt_ext;
 
     /* Cached real MSR permission bitmaps of the l2 guest */
     unsigned long *ns_cached_msrpm;
diff --git a/xen/include/asm-x86/hvm/svm/vmcb.h b/xen/include/asm-x86/hvm/svm/vmcb.h
index 01ce20b0bd..beec1f6c0e 100644
--- a/xen/include/asm-x86/hvm/svm/vmcb.h
+++ b/xen/include/asm-x86/hvm/svm/vmcb.h
@@ -358,9 +358,9 @@ typedef union
     u64 bytes;
     struct
     {
-        u64 enable:1;
+        u64 lbr_enable:1;
     } fields;
-} lbrctrl_t;
+} virt_ext_t;
 
 typedef union
 {
@@ -427,7 +427,7 @@ struct vmcb_struct {
     u64 res08[2];
     eventinj_t  eventinj;       /* offset 0xA8 */
     u64 _h_cr3;                 /* offset 0xB0 - cleanbit 4 */
-    lbrctrl_t lbr_control;      /* offset 0xB8 */
+    virt_ext_t virt_ext;        /* offset 0xB8 */
     vmcbcleanbits_t cleanbits;  /* offset 0xC0 */
     u32 res09;                  /* offset 0xC4 */
     u64 nextrip;                /* offset 0xC8 */
-- 
2.11.0


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[PATCH 2/3] x86/svm: add virtual VMLOAD/VMSAVE feature definition

[brian.woods]

From: Brian Woods <brian.woods@amd.com>

Adding support for enabling the virtual VMLOAD/VMSAVE feature..

Signed-off-by: Brian Woods <brian.woods@amd.com>
---
 xen/include/asm-x86/hvm/svm/svm.h  | 2 ++
 xen/include/asm-x86/hvm/svm/vmcb.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/xen/include/asm-x86/hvm/svm/svm.h b/xen/include/asm-x86/hvm/svm/svm.h
index 0956f860ef..4edf7b002d 100644
--- a/xen/include/asm-x86/hvm/svm/svm.h
+++ b/xen/include/asm-x86/hvm/svm/svm.h
@@ -64,6 +64,7 @@ extern u32 svm_feature_flags;
 #define SVM_FEATURE_FLUSHBYASID    6 /* TLB flush by ASID support */
 #define SVM_FEATURE_DECODEASSISTS  7 /* Decode assists support */
 #define SVM_FEATURE_PAUSEFILTER   10 /* Pause intercept filter support */
+#define SVM_FEATURE_VLOADSAVE     15 /* virtual vmload/vmsave */
 
 #define cpu_has_svm_feature(f) test_bit(f, &svm_feature_flags)
 #define cpu_has_svm_npt       cpu_has_svm_feature(SVM_FEATURE_NPT)
@@ -74,6 +75,7 @@ extern u32 svm_feature_flags;
 #define cpu_has_svm_decode    cpu_has_svm_feature(SVM_FEATURE_DECODEASSISTS)
 #define cpu_has_pause_filter  cpu_has_svm_feature(SVM_FEATURE_PAUSEFILTER)
 #define cpu_has_tsc_ratio     cpu_has_svm_feature(SVM_FEATURE_TSCRATEMSR)
+#define cpu_has_svm_vloadsave cpu_has_svm_feature(SVM_FEATURE_VLOADSAVE)
 
 #define SVM_PAUSEFILTER_INIT    3000
 
diff --git a/xen/include/asm-x86/hvm/svm/vmcb.h b/xen/include/asm-x86/hvm/svm/vmcb.h
index beec1f6c0e..1d3d45f6d7 100644
--- a/xen/include/asm-x86/hvm/svm/vmcb.h
+++ b/xen/include/asm-x86/hvm/svm/vmcb.h
@@ -359,6 +359,7 @@ typedef union
     struct
     {
         u64 lbr_enable:1;
+        u64 vloadsave_enable:1;
     } fields;
 } virt_ext_t;
 
-- 
2.11.0


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[PATCH 3/3] x86/svm: add virtual VMLOAD/VMSAVE support

[brian.woods]

From: Brian Woods <brian.woods@amd.com>

On AMD family 17h server processors, there is a feature called virtual
VMLOAD/VMSAVE.  This allows a nested hypervisor to preform a VMLOAD or
VMSAVE without needing to be intercepted by the host hypervisor.
Virtual VMLOAD/VMSAVE requires the host hypervisor to be in long mode
and nested page tables to be enabled.  For more information about it
please see:

AMD64 Architecture Programmer’s Manual Volume 2: System Programming
http://support.amd.com/TechDocs/24593.pdf
Section: VMSAVE and VMLOAD Virtualization (Section 15.33.1)

This patch series adds support to check for and enable the virtual
VMLOAD/VMSAVE features if available.

Signed-off-by: Brian Woods <brian.woods@amd.com>
---
 xen/arch/x86/hvm/svm/svm.c      | 1 +
 xen/arch/x86/hvm/svm/svmdebug.c | 2 ++
 xen/arch/x86/hvm/svm/vmcb.c     | 7 +++++++
 3 files changed, 10 insertions(+)

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index c8ffb17515..60b1288a31 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1669,6 +1669,7 @@ const struct hvm_function_table * __init start_svm(void)
     P(cpu_has_svm_nrips, "Next-RIP Saved on #VMEXIT");
     P(cpu_has_svm_cleanbits, "VMCB Clean Bits");
     P(cpu_has_svm_decode, "DecodeAssists");
+    P(cpu_has_svm_vloadsave, "Virtual VMLOAD/VMSAVE");
     P(cpu_has_pause_filter, "Pause-Intercept Filter");
     P(cpu_has_tsc_ratio, "TSC Rate MSR");
 #undef P
diff --git a/xen/arch/x86/hvm/svm/svmdebug.c b/xen/arch/x86/hvm/svm/svmdebug.c
index 89ef2db932..7145e2f5ca 100644
--- a/xen/arch/x86/hvm/svm/svmdebug.c
+++ b/xen/arch/x86/hvm/svm/svmdebug.c
@@ -55,6 +55,8 @@ void svm_vmcb_dump(const char *from, const struct vmcb_struct *vmcb)
            vmcb->exitinfo1, vmcb->exitinfo2);
     printk("np_enable = %#"PRIx64" guest_asid = %#x\n",
            vmcb_get_np_enable(vmcb), vmcb_get_guest_asid(vmcb));
+    printk("virtual vmload/vmsave = %d  virt_ext = %#"PRIx64"\n",
+           vmcb->virt_ext.fields.vloadsave_enable, vmcb->virt_ext.bytes);
     printk("cpl = %d efer = %#"PRIx64" star = %#"PRIx64" lstar = %#"PRIx64"\n",
            vmcb_get_cpl(vmcb), vmcb_get_efer(vmcb), vmcb->star, vmcb->lstar);
     printk("CR0 = 0x%016"PRIx64" CR2 = 0x%016"PRIx64"\n",
diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
index 997e7597e0..cc35d00bb7 100644
--- a/xen/arch/x86/hvm/svm/vmcb.c
+++ b/xen/arch/x86/hvm/svm/vmcb.c
@@ -200,6 +200,13 @@ static int construct_vmcb(struct vcpu *v)
 
         /* PAT is under complete control of SVM when using nested paging. */
         svm_disable_intercept_for_msr(v, MSR_IA32_CR_PAT);
+
+        /* use virtual VMLOAD/VMSAVE if available */
+        if (cpu_has_svm_vloadsave) {
+            vmcb->virt_ext.fields.vloadsave_enable = 1;
+            vmcb->_general2_intercepts &= ~GENERAL2_INTERCEPT_VMLOAD;
+            vmcb->_general2_intercepts &= ~GENERAL2_INTERCEPT_VMSAVE;
+        }
     }
     else
     {
-- 
2.11.0


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Re: [PATCH 3/3] x86/svm: add virtual VMLOAD/VMSAVE support

[Andrew Cooper]

On 31/10/17 22:03, brian.woods@amd.com wrote:
> From: Brian Woods <brian.woods@amd.com>
>
> On AMD family 17h server processors, there is a feature called virtual
> VMLOAD/VMSAVE.  This allows a nested hypervisor to preform a VMLOAD or
> VMSAVE without needing to be intercepted by the host hypervisor.
> Virtual VMLOAD/VMSAVE requires the host hypervisor to be in long mode
> and nested page tables to be enabled.  For more information about it
> please see:
>
> AMD64 Architecture Programmer’s Manual Volume 2: System Programming
> http://support.amd.com/TechDocs/24593.pdf
> Section: VMSAVE and VMLOAD Virtualization (Section 15.33.1)
>
> This patch series adds support to check for and enable the virtual
> VMLOAD/VMSAVE features if available.
>
> Signed-off-by: Brian Woods <brian.woods@amd.com>
> ---
>  xen/arch/x86/hvm/svm/svm.c      | 1 +
>  xen/arch/x86/hvm/svm/svmdebug.c | 2 ++
>  xen/arch/x86/hvm/svm/vmcb.c     | 7 +++++++
>  3 files changed, 10 insertions(+)
>
> diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
> index c8ffb17515..60b1288a31 100644
> --- a/xen/arch/x86/hvm/svm/svm.c
> +++ b/xen/arch/x86/hvm/svm/svm.c
> @@ -1669,6 +1669,7 @@ const struct hvm_function_table * __init start_svm(void)
>      P(cpu_has_svm_nrips, "Next-RIP Saved on #VMEXIT");
>      P(cpu_has_svm_cleanbits, "VMCB Clean Bits");
>      P(cpu_has_svm_decode, "DecodeAssists");
> +    P(cpu_has_svm_vloadsave, "Virtual VMLOAD/VMSAVE");
>      P(cpu_has_pause_filter, "Pause-Intercept Filter");
>      P(cpu_has_tsc_ratio, "TSC Rate MSR");
>  #undef P
> diff --git a/xen/arch/x86/hvm/svm/svmdebug.c b/xen/arch/x86/hvm/svm/svmdebug.c
> index 89ef2db932..7145e2f5ca 100644
> --- a/xen/arch/x86/hvm/svm/svmdebug.c
> +++ b/xen/arch/x86/hvm/svm/svmdebug.c
> @@ -55,6 +55,8 @@ void svm_vmcb_dump(const char *from, const struct vmcb_struct *vmcb)
>             vmcb->exitinfo1, vmcb->exitinfo2);
>      printk("np_enable = %#"PRIx64" guest_asid = %#x\n",
>             vmcb_get_np_enable(vmcb), vmcb_get_guest_asid(vmcb));
> +    printk("virtual vmload/vmsave = %d  virt_ext = %#"PRIx64"\n",
> +           vmcb->virt_ext.fields.vloadsave_enable, vmcb->virt_ext.bytes);
>      printk("cpl = %d efer = %#"PRIx64" star = %#"PRIx64" lstar = %#"PRIx64"\n",
>             vmcb_get_cpl(vmcb), vmcb_get_efer(vmcb), vmcb->star, vmcb->lstar);
>      printk("CR0 = 0x%016"PRIx64" CR2 = 0x%016"PRIx64"\n",
> diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
> index 997e7597e0..cc35d00bb7 100644
> --- a/xen/arch/x86/hvm/svm/vmcb.c
> +++ b/xen/arch/x86/hvm/svm/vmcb.c
> @@ -200,6 +200,13 @@ static int construct_vmcb(struct vcpu *v)
>  
>          /* PAT is under complete control of SVM when using nested paging. */
>          svm_disable_intercept_for_msr(v, MSR_IA32_CR_PAT);
> +
> +        /* use virtual VMLOAD/VMSAVE if available */
> +        if (cpu_has_svm_vloadsave) {

The style in this file is quite hit and miss, but we expect new code to
conform to the standards.  In this case, the correct style is:

if ( cpu_has_svm_vloadsave )
{

This can be fixed on commit if there are no other comments.

All 3 patches Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

~Andrew

> +            vmcb->virt_ext.fields.vloadsave_enable = 1;
> +            vmcb->_general2_intercepts &= ~GENERAL2_INTERCEPT_VMLOAD;
> +            vmcb->_general2_intercepts &= ~GENERAL2_INTERCEPT_VMSAVE;
> +        }
>      }
>      else
>      {


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Re: [PATCH 3/3] x86/svm: add virtual VMLOAD/VMSAVE support

[Brian Woods]

[-- Attachment #1: Type: text/plain, Size: 558 bytes --]

On Tue, Oct 31, 2017 at 10:15:08PM +0000, Andrew Cooper wrote:
> 
> The style in this file is quite hit and miss, but we expect new code to
> conform to the standards.  In this case, the correct style is:
> 
> if ( cpu_has_svm_vloadsave )
> {
> 
> This can be fixed on commit if there are no other comments.
> 
> All 3 patches Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
> 
> ~Andrew
> 

My mistake.  Years of lknf has made it a habit.  I'll make sure to
double check next time.  Attached is the git format-patch for that
commit.

-- 
Brian Woods

[-- Attachment #2: 0003-x86-svm-add-virtual-VMLOAD-VMSAVE-support.patch --]
[-- Type: text/x-diff, Size: 3260 bytes --]

>From b0d7916a5a35096cb7309922176631f7e57efdf1 Mon Sep 17 00:00:00 2001
From: Brian Woods <brian.woods@amd.com>
Date: Tue, 31 Oct 2017 14:13:01 -0500
Subject: [PATCH 3/3] x86/svm: add virtual VMLOAD/VMSAVE support
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On AMD family 17h server processors, there is a feature called virtual
VMLOAD/VMSAVE.  This allows a nested hypervisor to preform a VMLOAD or
VMSAVE without needing to be intercepted by the host hypervisor.
Virtual VMLOAD/VMSAVE requires the host hypervisor to be in long mode
and nested page tables to be enabled.  For more information about it
please see:

AMD64 Architecture Programmer’s Manual Volume 2: System Programming
http://support.amd.com/TechDocs/24593.pdf
Section: VMSAVE and VMLOAD Virtualization (Section 15.33.1)

This patch series adds support to check for and enable the virtual
VMLOAD/VMSAVE features if available.

Signed-off-by: Brian Woods <brian.woods@amd.com>
---
 xen/arch/x86/hvm/svm/svm.c      | 1 +
 xen/arch/x86/hvm/svm/svmdebug.c | 2 ++
 xen/arch/x86/hvm/svm/vmcb.c     | 8 ++++++++
 3 files changed, 11 insertions(+)

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index c8ffb17515..60b1288a31 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1669,6 +1669,7 @@ const struct hvm_function_table * __init start_svm(void)
     P(cpu_has_svm_nrips, "Next-RIP Saved on #VMEXIT");
     P(cpu_has_svm_cleanbits, "VMCB Clean Bits");
     P(cpu_has_svm_decode, "DecodeAssists");
+    P(cpu_has_svm_vloadsave, "Virtual VMLOAD/VMSAVE");
     P(cpu_has_pause_filter, "Pause-Intercept Filter");
     P(cpu_has_tsc_ratio, "TSC Rate MSR");
 #undef P
diff --git a/xen/arch/x86/hvm/svm/svmdebug.c b/xen/arch/x86/hvm/svm/svmdebug.c
index 89ef2db932..7145e2f5ca 100644
--- a/xen/arch/x86/hvm/svm/svmdebug.c
+++ b/xen/arch/x86/hvm/svm/svmdebug.c
@@ -55,6 +55,8 @@ void svm_vmcb_dump(const char *from, const struct vmcb_struct *vmcb)
            vmcb->exitinfo1, vmcb->exitinfo2);
     printk("np_enable = %#"PRIx64" guest_asid = %#x\n",
            vmcb_get_np_enable(vmcb), vmcb_get_guest_asid(vmcb));
+    printk("virtual vmload/vmsave = %d  virt_ext = %#"PRIx64"\n",
+           vmcb->virt_ext.fields.vloadsave_enable, vmcb->virt_ext.bytes);
     printk("cpl = %d efer = %#"PRIx64" star = %#"PRIx64" lstar = %#"PRIx64"\n",
            vmcb_get_cpl(vmcb), vmcb_get_efer(vmcb), vmcb->star, vmcb->lstar);
     printk("CR0 = 0x%016"PRIx64" CR2 = 0x%016"PRIx64"\n",
diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
index 997e7597e0..eccc1e28bf 100644
--- a/xen/arch/x86/hvm/svm/vmcb.c
+++ b/xen/arch/x86/hvm/svm/vmcb.c
@@ -200,6 +200,14 @@ static int construct_vmcb(struct vcpu *v)
 
         /* PAT is under complete control of SVM when using nested paging. */
         svm_disable_intercept_for_msr(v, MSR_IA32_CR_PAT);
+
+        /* use virtual VMLOAD/VMSAVE if available */
+        if ( cpu_has_svm_vloadsave )
+        {
+            vmcb->virt_ext.fields.vloadsave_enable = 1;
+            vmcb->_general2_intercepts &= ~GENERAL2_INTERCEPT_VMLOAD;
+            vmcb->_general2_intercepts &= ~GENERAL2_INTERCEPT_VMSAVE;
+        }
     }
     else
     {
-- 
2.11.0


[-- Attachment #3: Type: text/plain, Size: 127 bytes --]

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Re: [PATCH 0/3] x86/svm: virtual VMLOAD/VMSAVE

[Boris Ostrovsky]

On 10/31/2017 06:03 PM, brian.woods@amd.com wrote:
> From: Brian Woods <brian.woods@amd.com>
>
> x86/svm: virtual VMLOAD/VMSAVE
>
> On AMD family 17h server processors, there is a feature called virtual
> VMLOAD/VMSAVE.  This allows a nested hypervisor to preform a VMLOAD or
> VMSAVE without needing to be intercepted by the host hypervisor.
> Virtual VMLOAD/VMSAVE requires the host hypervisor to be in long mode
> and nested page tables to be enabled.  For more information about it
> please see:
>
> AMD64 Architecture Programmer’s Manual Volume 2: System Programming
> http://support.amd.com/TechDocs/24593.pdf
> Section: VMSAVE and VMLOAD Virtualization (Section 15.33.1)
>
> This patch series adds support to check for and enable the virtual
> VMLOAD/VMSAVE features if available.
>
> Signed-off-by: Brian Woods <brian.woods@amd.com>
>
> Brian Woods (3):
>   x86/svm: rename lbr control field in vmcb
>   x86/svm: add virtual VMLOAD/VMSAVE feature definition
>   x86/svm: add virtual VMLOAD/VMSAVE support
>
>  xen/arch/x86/hvm/svm/nestedsvm.c        | 10 +++++-----
>  xen/arch/x86/hvm/svm/svm.c              |  3 ++-
>  xen/arch/x86/hvm/svm/svmdebug.c         |  2 ++
>  xen/arch/x86/hvm/svm/vmcb.c             |  7 +++++++
>  xen/include/asm-x86/hvm/svm/nestedsvm.h |  4 ++--
>  xen/include/asm-x86/hvm/svm/svm.h       |  2 ++
>  xen/include/asm-x86/hvm/svm/vmcb.h      |  7 ++++---
>  7 files changed, 24 insertions(+), 11 deletions(-)
>


Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

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Re: [PATCH 0/3] x86/svm: virtual VMLOAD/VMSAVE

[Andrew Cooper]

On 01/11/17 17:00, Boris Ostrovsky wrote:
> On 10/31/2017 06:03 PM, brian.woods@amd.com wrote:
>> From: Brian Woods <brian.woods@amd.com>
>>
>> x86/svm: virtual VMLOAD/VMSAVE
>>
>> On AMD family 17h server processors, there is a feature called virtual
>> VMLOAD/VMSAVE.  This allows a nested hypervisor to preform a VMLOAD or
>> VMSAVE without needing to be intercepted by the host hypervisor.
>> Virtual VMLOAD/VMSAVE requires the host hypervisor to be in long mode
>> and nested page tables to be enabled.  For more information about it
>> please see:
>>
>> AMD64 Architecture Programmer’s Manual Volume 2: System Programming
>> http://support.amd.com/TechDocs/24593.pdf
>> Section: VMSAVE and VMLOAD Virtualization (Section 15.33.1)
>>
>> This patch series adds support to check for and enable the virtual
>> VMLOAD/VMSAVE features if available.
>>
>> Signed-off-by: Brian Woods <brian.woods@amd.com>
>>
>> Brian Woods (3):
>>   x86/svm: rename lbr control field in vmcb
>>   x86/svm: add virtual VMLOAD/VMSAVE feature definition
>>   x86/svm: add virtual VMLOAD/VMSAVE support
>>
>>  xen/arch/x86/hvm/svm/nestedsvm.c        | 10 +++++-----
>>  xen/arch/x86/hvm/svm/svm.c              |  3 ++-
>>  xen/arch/x86/hvm/svm/svmdebug.c         |  2 ++
>>  xen/arch/x86/hvm/svm/vmcb.c             |  7 +++++++
>>  xen/include/asm-x86/hvm/svm/nestedsvm.h |  4 ++--
>>  xen/include/asm-x86/hvm/svm/svm.h       |  2 ++
>>  xen/include/asm-x86/hvm/svm/vmcb.h      |  7 ++++---
>>  7 files changed, 24 insertions(+), 11 deletions(-)
>>
>
> Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

I've given these a spin on my Zen box, although nothing nested-virt
specific.

I've pulled the series into x86-next.

~Andrew

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