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From: Ryan Chen <ryan_chen@aspeedtech.com>
To: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>, Brendan Higgins
 <brendanhiggins@google.com>, Benjamin Herrenschmidt
 <benh@kernel.crashing.org>, C?ric Le Goater <clg@kaod.org>, Joel Stanley
 <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>
CC: "openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>
Subject: RE: [RFC PATCH dev-5.1 3/6] irqchip/aspeed-i2c-ic: add I2C SRAM
 enabling control
Thread-Topic: [RFC PATCH dev-5.1 3/6] irqchip/aspeed-i2c-ic: add I2C SRAM
 enabling control
Thread-Index: AQHVJ6HvLShnZ8JPmk6GW8AjxYiUw6alQa9w
Date: Fri, 21 Jun 2019 00:33:18 +0000
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References: <20190620194922.15093-1-jae.hyun.yoo@linux.intel.com>
 <20190620194922.15093-4-jae.hyun.yoo@linux.intel.com>
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Hello Jae,
	The i2c register setting must after scu reset. - APEED_I2C_SRAM_BUFFER_EN
	My recommend aspeed-i2c-ic.c need be probe after scu reset. And all others=
 i2c bus is no needed for scu reset.=20

Ryan=20

-----Original Message-----
From: openbmc [mailto:openbmc-bounces+ryan_chen=3Daspeedtech.com@lists.ozla=
bs.org] On Behalf Of Jae Hyun Yoo
Sent: Friday, June 21, 2019 3:49 AM
To: Brendan Higgins <brendanhiggins@google.com>; Benjamin Herrenschmidt <be=
nh@kernel.crashing.org>; C?ric Le Goater <clg@kaod.org>; Joel Stanley <joel=
@jms.id.au>; Andrew Jeffery <andrew@aj.id.au>
Cc: openbmc@lists.ozlabs.org; Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Subject: [RFC PATCH dev-5.1 3/6] irqchip/aspeed-i2c-ic: add I2C SRAM enabli=
ng control

This commit adds I2C SRAM enabling control for AST2500 SoC to support buffe=
r mode and DMA mode transfer. The SRAM is enabled by default in AST2400 SoC=
.

Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
---
 drivers/irqchip/irq-aspeed-i2c-ic.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/irqchip/irq-aspeed-i2c-ic.c b/drivers/irqchip/irq-aspe=
ed-i2c-ic.c
index f20200af0992..99985b22a9fa 100644
--- a/drivers/irqchip/irq-aspeed-i2c-ic.c
+++ b/drivers/irqchip/irq-aspeed-i2c-ic.c
@@ -18,6 +18,9 @@
 #include <linux/of_irq.h>
 #include <linux/io.h>
=20
+/* I2C Global Control Register (AST2500) */
+#define ASPEED_I2C_GLOBAL_CTRL_REG	0xc
+#define  ASPEED_I2C_SRAM_BUFFER_EN	BIT(0)
=20
 #define ASPEED_I2C_IC_NUM_BUS 14
=20
@@ -100,6 +103,11 @@ static int __init aspeed_i2c_ic_of_init(struct device_=
node *node,
 	irq_set_chained_handler_and_data(i2c_ic->parent_irq,
 					 aspeed_i2c_ic_irq_handler, i2c_ic);
=20
+	/* Enable I2C SRAM buffer in case of AST2500 */
+	if (of_device_is_compatible(node, "aspeed,ast2500-i2c-ic"))
+		writel(ASPEED_I2C_SRAM_BUFFER_EN,
+		       i2c_ic->base + ASPEED_I2C_GLOBAL_CTRL_REG);
+
 	pr_info("i2c controller registered, irq %d\n", i2c_ic->parent_irq);
=20
 	return 0;
--
2.22.0