* [PATCH v4 0/8] drm/i915: GTT remapping for display
@ 2019-05-09 12:21 Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 1/8] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
` (11 more replies)
0 siblings, 12 replies; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Here's a new version of the GTT remapping series.
Changes since last time:
- Split up some code shuffling from the main patch
- Made the dumb stride alignment proper
- Finished the test case
- Fixed a few bugs found in testing
The one thing I didn't do is make remapping always happen.
The main reason is that it would break FBC, and I don't
want to rewrite the FBC code right now.
Test-with: 20190508162906.20808-1-ville.syrjala@linux.intel.com
Ville Syrjälä (8):
drm/i915: Add a new "remapped" gtt_view
drm/i915/selftests: Add mock selftest for remapped vmas
drm/i915/selftests: Add live vma selftest
drm/i915: Shuffle stride checking code around
drm/i915: Overcome display engine stride limits via GTT remapping
drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping
drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for
gen7+
drm/i915: Bump gen7+ fb size limits to 16kx16k
drivers/gpu/drm/i915/i915_debugfs.c | 12 +
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_gem.c | 43 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 88 ++++
drivers/gpu/drm/i915/i915_gem_gtt.h | 25 +-
drivers/gpu/drm/i915/i915_vma.c | 10 +-
drivers/gpu/drm/i915/i915_vma.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 453 ++++++++++++++----
drivers/gpu/drm/i915/intel_display.h | 4 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_sprite.c | 34 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 246 +++++++++-
13 files changed, 798 insertions(+), 126 deletions(-)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v4 1/8] drm/i915: Add a new "remapped" gtt_view
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
@ 2019-05-09 12:21 ` Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 2/8] drm/i915/selftests: Add mock selftest for remapped vmas Ville Syrjala
` (10 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To overcome display engine stride limits we'll want to remap the
pages in the GTT. To that end we need a new gtt_view type which
is just like the "rotated" type except not rotated.
v2: Use intel_remapped_plane_info base type
s/unused/unused_mbz/ (Chris)
Separate BUILD_BUG_ON()s (Chris)
Use I915_GTT_PAGE_SIZE (Chris)
v3: Use i915_gem_object_get_dma_address() (Chris)
Trim the sg (Tvrtko)
v4: Actually trim this time. Limit the max length
to one row of pages to keep things simple
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 ++++
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_gem.c | 17 ++++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 88 +++++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_gtt.h | 25 +++++--
drivers/gpu/drm/i915/i915_vma.c | 6 +-
drivers/gpu/drm/i915/i915_vma.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 11 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 6 +-
10 files changed, 163 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 072464a18050..633a08c0f907 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -212,6 +212,18 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
vma->ggtt_view.rotated.plane[1].offset);
break;
+ case I915_GGTT_VIEW_REMAPPED:
+ seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
+ vma->ggtt_view.remapped.plane[0].width,
+ vma->ggtt_view.remapped.plane[0].height,
+ vma->ggtt_view.remapped.plane[0].stride,
+ vma->ggtt_view.remapped.plane[0].offset,
+ vma->ggtt_view.remapped.plane[1].width,
+ vma->ggtt_view.remapped.plane[1].height,
+ vma->ggtt_view.remapped.plane[1].stride,
+ vma->ggtt_view.remapped.plane[1].offset);
+ break;
+
default:
MISSING_CASE(vma->ggtt_view.type);
break;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d0257808734c..c6d519e67ed0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2859,6 +2859,10 @@ i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
unsigned int n);
dma_addr_t
+i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned int *len);
+dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
unsigned long n);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2fcec1bfb038..4e474bcf4c22 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5081,16 +5081,29 @@ i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
}
dma_addr_t
-i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
- unsigned long n)
+i915_gem_object_get_dma_address_len(struct drm_i915_gem_object *obj,
+ unsigned long n,
+ unsigned int *len)
{
struct scatterlist *sg;
unsigned int offset;
sg = i915_gem_object_get_sg(obj, n, &offset);
+
+ if (len)
+ *len = sg_dma_len(sg) - (offset << PAGE_SHIFT);
+
return sg_dma_address(sg) + (offset << PAGE_SHIFT);
}
+dma_addr_t
+i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
+ unsigned long n)
+{
+ return i915_gem_object_get_dma_address_len(obj, n, NULL);
+}
+
+
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
{
struct sg_table *pages;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8f5db787b7f2..9ed41aefb456 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3608,6 +3608,89 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
return ERR_PTR(ret);
}
+static struct scatterlist *
+remap_pages(struct drm_i915_gem_object *obj, unsigned int offset,
+ unsigned int width, unsigned int height,
+ unsigned int stride,
+ struct sg_table *st, struct scatterlist *sg)
+{
+ unsigned int row;
+
+ for (row = 0; row < height; row++) {
+ unsigned int left = width * I915_GTT_PAGE_SIZE;
+
+ while (left) {
+ dma_addr_t addr;
+ unsigned int length;
+
+ /* We don't need the pages, but need to initialize
+ * the entries so the sg list can be happily traversed.
+ * The only thing we need are DMA addresses.
+ */
+
+ addr = i915_gem_object_get_dma_address_len(obj, offset, &length);
+
+ length = min(left, length);
+
+ st->nents++;
+
+ sg_set_page(sg, NULL, length, 0);
+ sg_dma_address(sg) = addr;
+ sg_dma_len(sg) = length;
+ sg = sg_next(sg);
+
+ offset += length / I915_GTT_PAGE_SIZE;
+ left -= length;
+ }
+
+ offset += stride - width;
+ }
+
+ return sg;
+}
+
+static noinline struct sg_table *
+intel_remap_pages(struct intel_remapped_info *rem_info,
+ struct drm_i915_gem_object *obj)
+{
+ unsigned int size = intel_remapped_info_size(rem_info);
+ struct sg_table *st;
+ struct scatterlist *sg;
+ int ret = -ENOMEM;
+ int i;
+
+ /* Allocate target SG list. */
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ goto err_st_alloc;
+
+ ret = sg_alloc_table(st, size, GFP_KERNEL);
+ if (ret)
+ goto err_sg_alloc;
+
+ st->nents = 0;
+ sg = st->sgl;
+
+ for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
+ sg = remap_pages(obj, rem_info->plane[i].offset,
+ rem_info->plane[i].width, rem_info->plane[i].height,
+ rem_info->plane[i].stride, st, sg);
+ }
+
+ i915_sg_trim(st);
+
+ return st;
+
+err_sg_alloc:
+ kfree(st);
+err_st_alloc:
+
+ DRM_DEBUG_DRIVER("Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
+ obj->base.size, rem_info->plane[0].width, rem_info->plane[0].height, size);
+
+ return ERR_PTR(ret);
+}
+
static noinline struct sg_table *
intel_partial_pages(const struct i915_ggtt_view *view,
struct drm_i915_gem_object *obj)
@@ -3686,6 +3769,11 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
break;
+ case I915_GGTT_VIEW_REMAPPED:
+ vma->pages =
+ intel_remap_pages(&vma->ggtt_view.remapped, vma->obj);
+ break;
+
case I915_GGTT_VIEW_PARTIAL:
vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
break;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 2fafa04c45ec..98fc71053f7c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -163,11 +163,18 @@ typedef u64 gen8_ppgtt_pml4e_t;
struct sg_table;
+struct intel_remapped_plane_info {
+ /* in gtt pages */
+ unsigned int width, height, stride, offset;
+} __packed;
+
+struct intel_remapped_info {
+ struct intel_remapped_plane_info plane[2];
+ unsigned int unused_mbz;
+} __packed;
+
struct intel_rotation_info {
- struct intel_rotation_plane_info {
- /* tiles */
- unsigned int width, height, stride, offset;
- } plane[2];
+ struct intel_remapped_plane_info plane[2];
} __packed;
struct intel_partial_info {
@@ -179,12 +186,20 @@ enum i915_ggtt_view_type {
I915_GGTT_VIEW_NORMAL = 0,
I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
+ I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
};
static inline void assert_i915_gem_gtt_types(void)
{
BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
+
+ /* Check that rotation/remapped shares offsets for simplicity */
+ BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=
+ offsetof(struct intel_rotation_info, plane[0]));
+ BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=
+ offsetofend(struct intel_rotation_info, plane[1]));
/* As we encode the size of each branch inside the union into its type,
* we have to be careful that each branch has a unique size.
@@ -193,6 +208,7 @@ static inline void assert_i915_gem_gtt_types(void)
case I915_GGTT_VIEW_NORMAL:
case I915_GGTT_VIEW_PARTIAL:
case I915_GGTT_VIEW_ROTATED:
+ case I915_GGTT_VIEW_REMAPPED:
/* gcc complains if these are identical cases */
break;
}
@@ -204,6 +220,7 @@ struct i915_ggtt_view {
/* Members need to contain no holes/padding */
struct intel_partial_info partial;
struct intel_rotation_info rotated;
+ struct intel_remapped_info remapped;
};
};
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index d4d308b6d1d8..c68b435d4064 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -159,6 +159,9 @@ vma_create(struct drm_i915_gem_object *obj,
} else if (view->type == I915_GGTT_VIEW_ROTATED) {
vma->size = intel_rotation_info_size(&view->rotated);
vma->size <<= PAGE_SHIFT;
+ } else if (view->type == I915_GGTT_VIEW_REMAPPED) {
+ vma->size = intel_remapped_info_size(&view->remapped);
+ vma->size <<= PAGE_SHIFT;
}
}
@@ -484,7 +487,8 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
* Explicitly disable for rotated VMA since the display does not
* need the fence and the VMA is not accessible to other users.
*/
- if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
+ if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
+ vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
return;
fenceable = (vma->node.size >= vma->fence_size &&
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 6eab70953a57..8543d2953cd1 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -277,8 +277,11 @@ i915_vma_compare(struct i915_vma *vma,
*/
BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL >= I915_GGTT_VIEW_PARTIAL);
BUILD_BUG_ON(I915_GGTT_VIEW_PARTIAL >= I915_GGTT_VIEW_ROTATED);
+ BUILD_BUG_ON(I915_GGTT_VIEW_ROTATED >= I915_GGTT_VIEW_REMAPPED);
BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
offsetof(typeof(*view), partial));
+ BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
+ offsetof(typeof(*view), remapped));
return memcmp(&vma->ggtt_view.partial, &view->partial, view->type);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a351c8e219ba..0931fe621077 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1997,6 +1997,17 @@ unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info
return size;
}
+unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
+{
+ unsigned int size = 0;
+ int i;
+
+ for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
+ size += rem_info->plane[i].width * rem_info->plane[i].height;
+
+ return size;
+}
+
static void
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
const struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 247893ed1543..5d28bd3a4a42 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1461,6 +1461,7 @@ unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
void intel_add_fb_offsets(int *x, int *y,
const struct intel_plane_state *state, int plane);
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
+unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
void intel_mark_busy(struct drm_i915_private *dev_priv);
void intel_mark_idle(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index fc594b030f5a..18dc221cb22b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -397,8 +397,8 @@ assert_rotated(struct drm_i915_gem_object *obj,
return sg;
}
-static unsigned int rotated_size(const struct intel_rotation_plane_info *a,
- const struct intel_rotation_plane_info *b)
+static unsigned int rotated_size(const struct intel_remapped_plane_info *a,
+ const struct intel_remapped_plane_info *b)
{
return a->width * a->height + b->width * b->height;
}
@@ -408,7 +408,7 @@ static int igt_vma_rotate(void *arg)
struct i915_ggtt *ggtt = arg;
struct i915_address_space *vm = &ggtt->vm;
struct drm_i915_gem_object *obj;
- const struct intel_rotation_plane_info planes[] = {
+ const struct intel_remapped_plane_info planes[] = {
{ .width = 1, .height = 1, .stride = 1 },
{ .width = 2, .height = 2, .stride = 2 },
{ .width = 4, .height = 4, .stride = 4 },
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 2/8] drm/i915/selftests: Add mock selftest for remapped vmas
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 1/8] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
@ 2019-05-09 12:21 ` Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 3/8] drm/i915/selftests: Add live vma selftest Ville Syrjala
` (9 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extend the rotated vma mock selftest to cover remapped vmas as
well.
TODO: reindent the loops I guess? Left like this for now to
ease review
v2: Include the vma type in the error message (Chris)
v3: Deal with trimmed sg
v4: Drop leftover debugs
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/selftests/i915_vma.c | 98 +++++++++++++++++++++--
1 file changed, 90 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 18dc221cb22b..89f6ef945c1b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -59,7 +59,7 @@ static bool assert_vma(struct i915_vma *vma,
static struct i915_vma *
checked_vma_instance(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
- struct i915_ggtt_view *view)
+ const struct i915_ggtt_view *view)
{
struct i915_vma *vma;
bool ok = true;
@@ -397,13 +397,74 @@ assert_rotated(struct drm_i915_gem_object *obj,
return sg;
}
+static unsigned long remapped_index(const struct intel_remapped_info *r,
+ unsigned int n,
+ unsigned int x,
+ unsigned int y)
+{
+ return (r->plane[n].stride * y +
+ r->plane[n].offset + x);
+}
+
+static struct scatterlist *
+assert_remapped(struct drm_i915_gem_object *obj,
+ const struct intel_remapped_info *r, unsigned int n,
+ struct scatterlist *sg)
+{
+ unsigned int x, y;
+ unsigned int left = 0;
+ unsigned int offset;
+
+ for (y = 0; y < r->plane[n].height; y++) {
+ for (x = 0; x < r->plane[n].width; x++) {
+ unsigned long src_idx;
+ dma_addr_t src;
+
+ if (!sg) {
+ pr_err("Invalid sg table: too short at plane %d, (%d, %d)!\n",
+ n, x, y);
+ return ERR_PTR(-EINVAL);
+ }
+ if (!left) {
+ offset = 0;
+ left = sg_dma_len(sg);
+ }
+
+ src_idx = remapped_index(r, n, x, y);
+ src = i915_gem_object_get_dma_address(obj, src_idx);
+
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
+ pr_err("Invalid sg.length, found %d, expected %lu for remapped page (%d, %d) [src index %lu]\n",
+ sg_dma_len(sg), PAGE_SIZE,
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (sg_dma_address(sg) + offset != src) {
+ pr_err("Invalid address for remapped page (%d, %d) [src index %lu]\n",
+ x, y, src_idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ left -= PAGE_SIZE;
+ offset += PAGE_SIZE;
+
+
+ if (!left)
+ sg = sg_next(sg);
+ }
+ }
+
+ return sg;
+}
+
static unsigned int rotated_size(const struct intel_remapped_plane_info *a,
const struct intel_remapped_plane_info *b)
{
return a->width * a->height + b->width * b->height;
}
-static int igt_vma_rotate(void *arg)
+static int igt_vma_rotate_remap(void *arg)
{
struct i915_ggtt *ggtt = arg;
struct i915_address_space *vm = &ggtt->vm;
@@ -426,6 +487,11 @@ static int igt_vma_rotate(void *arg)
{ .width = 6, .height = 4, .stride = 6 },
{ }
}, *a, *b;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
const unsigned int max_pages = 64;
int err = -ENOMEM;
@@ -437,6 +503,7 @@ static int igt_vma_rotate(void *arg)
if (IS_ERR(obj))
goto out;
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
for (b = planes + ARRAY_SIZE(planes); b-- != planes; ) {
struct i915_ggtt_view view;
@@ -447,7 +514,7 @@ static int igt_vma_rotate(void *arg)
GEM_BUG_ON(max_offset > max_pages);
max_offset = max_pages - max_offset;
- view.type = I915_GGTT_VIEW_ROTATED;
+ view.type = *t;
view.rotated.plane[0] = *a;
view.rotated.plane[1] = *b;
@@ -468,14 +535,23 @@ static int igt_vma_rotate(void *arg)
goto out_object;
}
- if (vma->size != rotated_size(a, b) * PAGE_SIZE) {
+ if (view.type == I915_GGTT_VIEW_ROTATED &&
+ vma->size != rotated_size(a, b) * PAGE_SIZE) {
pr_err("VMA is wrong size, expected %lu, found %llu\n",
PAGE_SIZE * rotated_size(a, b), vma->size);
err = -EINVAL;
goto out_object;
}
- if (vma->pages->nents != rotated_size(a, b)) {
+ if (view.type == I915_GGTT_VIEW_REMAPPED &&
+ vma->size > rotated_size(a, b) * PAGE_SIZE) {
+ pr_err("VMA is wrong size, expected %lu, found %llu\n",
+ PAGE_SIZE * rotated_size(a, b), vma->size);
+ err = -EINVAL;
+ goto out_object;
+ }
+
+ if (vma->pages->nents > rotated_size(a, b)) {
pr_err("sg table is wrong sizeo, expected %u, found %u nents\n",
rotated_size(a, b), vma->pages->nents);
err = -EINVAL;
@@ -497,9 +573,14 @@ static int igt_vma_rotate(void *arg)
sg = vma->pages->sgl;
for (n = 0; n < ARRAY_SIZE(view.rotated.plane); n++) {
- sg = assert_rotated(obj, &view.rotated, n, sg);
+ if (view.type == I915_GGTT_VIEW_ROTATED)
+ sg = assert_rotated(obj, &view.rotated, n, sg);
+ else
+ sg = assert_remapped(obj, &view.remapped, n, sg);
if (IS_ERR(sg)) {
- pr_err("Inconsistent VMA pages for plane %d: [(%d, %d, %d, %d), (%d, %d, %d, %d)]\n", n,
+ pr_err("Inconsistent %s VMA pages for plane %d: [(%d, %d, %d, %d), (%d, %d, %d, %d)]\n",
+ view.type == I915_GGTT_VIEW_ROTATED ?
+ "rotated" : "remapped", n,
view.rotated.plane[0].width,
view.rotated.plane[0].height,
view.rotated.plane[0].stride,
@@ -518,6 +599,7 @@ static int igt_vma_rotate(void *arg)
}
}
}
+ }
out_object:
i915_gem_object_put(obj);
@@ -721,7 +803,7 @@ int i915_vma_mock_selftests(void)
static const struct i915_subtest tests[] = {
SUBTEST(igt_vma_create),
SUBTEST(igt_vma_pin1),
- SUBTEST(igt_vma_rotate),
+ SUBTEST(igt_vma_rotate_remap),
SUBTEST(igt_vma_partial),
};
struct drm_i915_private *i915;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 3/8] drm/i915/selftests: Add live vma selftest
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 1/8] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 2/8] drm/i915/selftests: Add mock selftest for remapped vmas Ville Syrjala
@ 2019-05-09 12:21 ` Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 4/8] drm/i915: Shuffle stride checking code around Ville Syrjala
` (8 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a live selftest to excercise rotated/remapped vmas. We simply
write through the rotated/remapped vma, and confirm that the data
appears in the right page when read through the normal vma.
Not sure what the fallout of making all rotated/remapped vmas
mappable/fenceable would be, hence I just hacked it in the test.
v2: Grab rpm reference (Chris)
GEM_BUG_ON(view.type not as expected) (Chris)
Allow CAN_FENCE for rotated/remapped vmas (Chris)
Update intel_plane_uses_fence() to ask for a fence
only for normal vmas on gen4+
v3: Deal with intel_wakeref_t
v4: Rebase
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_vma.c | 8 -
drivers/gpu/drm/i915/intel_display.c | 4 +-
.../drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 142 ++++++++++++++++++
4 files changed, 146 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index c68b435d4064..343736b2d602 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -483,14 +483,6 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
GEM_BUG_ON(!i915_vma_is_ggtt(vma));
GEM_BUG_ON(!vma->fence_size);
- /*
- * Explicitly disable for rotated VMA since the display does not
- * need the fence and the VMA is not accessible to other users.
- */
- if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
- vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
- return;
-
fenceable = (vma->node.size >= vma->fence_size &&
IS_ALIGNED(vma->node.start, vma->fence_alignment));
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0931fe621077..f4e6e9a8bbf9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2077,7 +2077,9 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- return INTEL_GEN(dev_priv) < 4 || plane->has_fbc;
+ return INTEL_GEN(dev_priv) < 4 ||
+ (plane->has_fbc &&
+ plane_state->view.type == I915_GGTT_VIEW_NORMAL);
}
struct i915_vma *
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 6d766925ad04..a54f590788a4 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -17,6 +17,7 @@ selftest(requests, i915_request_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(dmabuf, i915_gem_dmabuf_live_selftests)
+selftest(vma, i915_vma_live_selftests)
selftest(coherency, i915_gem_coherency_live_selftests)
selftest(gtt, i915_gem_gtt_live_selftests)
selftest(gem, i915_gem_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 89f6ef945c1b..0027c1fac336 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -834,3 +834,145 @@ int i915_vma_mock_selftests(void)
drm_dev_put(&i915->drm);
return err;
}
+
+static int igt_vma_remapped_gtt(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const struct intel_remapped_plane_info planes[] = {
+ { .width = 1, .height = 1, .stride = 1 },
+ { .width = 2, .height = 2, .stride = 2 },
+ { .width = 4, .height = 4, .stride = 4 },
+ { .width = 8, .height = 8, .stride = 8 },
+
+ { .width = 3, .height = 5, .stride = 3 },
+ { .width = 3, .height = 5, .stride = 4 },
+ { .width = 3, .height = 5, .stride = 5 },
+
+ { .width = 5, .height = 3, .stride = 5 },
+ { .width = 5, .height = 3, .stride = 7 },
+ { .width = 5, .height = 3, .stride = 9 },
+
+ { .width = 4, .height = 6, .stride = 6 },
+ { .width = 6, .height = 4, .stride = 6 },
+ { }
+ }, *p;
+ enum i915_ggtt_view_type types[] = {
+ I915_GGTT_VIEW_ROTATED,
+ I915_GGTT_VIEW_REMAPPED,
+ 0,
+ }, *t;
+ struct drm_i915_gem_object *obj;
+ intel_wakeref_t wakeref;
+ int err = 0;
+
+ obj = i915_gem_object_create_internal(i915, 10 * 10 * PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ mutex_lock(&i915->drm.struct_mutex);
+
+ wakeref = intel_runtime_pm_get(i915);
+
+ for (t = types; *t; t++) {
+ for (p = planes; p->width; p++) {
+ struct i915_ggtt_view view = {
+ .type = *t,
+ .rotated.plane[0] = *p,
+ };
+ struct i915_vma *vma;
+ u32 __iomem *map;
+ unsigned int x, y;
+ int err;
+
+ err = i915_gem_object_set_to_gtt_domain(obj, true);
+ if (err)
+ goto out;
+
+ vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out;
+ }
+
+ GEM_BUG_ON(vma->ggtt_view.type != *t);
+
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
+
+ for (y = 0 ; y < p->height; y++) {
+ for (x = 0 ; x < p->width; x++) {
+ unsigned int offset;
+ u32 val = y << 16 | x;
+
+ if (*t == I915_GGTT_VIEW_ROTATED)
+ offset = (x * p->height + y) * PAGE_SIZE;
+ else
+ offset = (y * p->width + x) * PAGE_SIZE;
+
+ iowrite32(val, &map[offset / sizeof(*map)]);
+ }
+ }
+
+ i915_vma_unpin_iomap(vma);
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto out;
+ }
+
+ GEM_BUG_ON(vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL);
+
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map)) {
+ err = PTR_ERR(map);
+ goto out;
+ }
+
+ for (y = 0 ; y < p->height; y++) {
+ for (x = 0 ; x < p->width; x++) {
+ unsigned int offset, src_idx;
+ u32 exp = y << 16 | x;
+ u32 val;
+
+ if (*t == I915_GGTT_VIEW_ROTATED)
+ src_idx = rotated_index(&view.rotated, 0, x, y);
+ else
+ src_idx = remapped_index(&view.remapped, 0, x, y);
+ offset = src_idx * PAGE_SIZE;
+
+ val = ioread32(&map[offset / sizeof(*map)]);
+ if (val != exp) {
+ pr_err("%s VMA write test failed, expected 0x%x, found 0x%x\n",
+ *t == I915_GGTT_VIEW_ROTATED ? "Rotated" : "Remapped",
+ val, exp);
+ i915_vma_unpin_iomap(vma);
+ goto out;
+ }
+ }
+ }
+ i915_vma_unpin_iomap(vma);
+ }
+ }
+
+out:
+ intel_runtime_pm_put(i915, wakeref);
+ mutex_unlock(&i915->drm.struct_mutex);
+ i915_gem_object_put(obj);
+
+ return err;
+}
+
+int i915_vma_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_vma_remapped_gtt),
+ };
+
+ return i915_subtests(tests, i915);
+}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 4/8] drm/i915: Shuffle stride checking code around
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (2 preceding siblings ...)
2019-05-09 12:21 ` [PATCH v4 3/8] drm/i915/selftests: Add live vma selftest Ville Syrjala
@ 2019-05-09 12:21 ` Ville Syrjala
2019-05-10 8:37 ` Daniel Vetter
2019-05-09 12:21 ` [PATCH v4 5/8] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
` (7 subsequent siblings)
11 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reorganize some fb stride checking code a bit to prepare for
gtt remapping. And do a bit of s/pitch/stride/ renaming in the
process for a bit more uniformity (apart from the whole
fb->pitches[] thing).
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 64 ++++++++++++++--------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f4e6e9a8bbf9..321cb6d2bc76 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2509,6 +2509,33 @@ bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
+static
+u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
+
+ /*
+ * We assume the primary plane for pipe A has
+ * the highest stride limits of them all.
+ */
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ plane = to_intel_plane(crtc->base.primary);
+
+ return plane->max_stride(plane, pixel_format, modifier,
+ DRM_MODE_ROTATE_0);
+}
+
+static u32
+intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
+{
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+ return 64;
+ else
+ return intel_tile_width_bytes(fb, color_plane);
+}
+
static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
struct drm_framebuffer *fb)
@@ -3586,15 +3613,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
-static u32
-intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
-{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 64;
- else
- return intel_tile_width_bytes(fb, color_plane);
-}
-
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
{
struct drm_device *dev = intel_crtc->base.dev;
@@ -14921,31 +14939,13 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
.dirty = intel_user_framebuffer_dirty,
};
-static
-u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
- u32 pixel_format, u64 fb_modifier)
-{
- struct intel_crtc *crtc;
- struct intel_plane *plane;
-
- /*
- * We assume the primary plane for pipe A has
- * the highest stride limits of them all.
- */
- crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
- plane = to_intel_plane(crtc->base.primary);
-
- return plane->max_stride(plane, pixel_format, fb_modifier,
- DRM_MODE_ROTATE_0);
-}
-
static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd)
{
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct drm_framebuffer *fb = &intel_fb->base;
- u32 pitch_limit;
+ u32 max_stride;
unsigned int tiling, stride;
int ret = -EINVAL;
int i;
@@ -14997,13 +14997,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
- pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
- mode_cmd->modifier[0]);
- if (mode_cmd->pitches[0] > pitch_limit) {
+ max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
+ mode_cmd->modifier[0]);
+ if (mode_cmd->pitches[0] > max_stride) {
DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
"tiled" : "linear",
- mode_cmd->pitches[0], pitch_limit);
+ mode_cmd->pitches[0], max_stride);
goto err;
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 5/8] drm/i915: Overcome display engine stride limits via GTT remapping
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (3 preceding siblings ...)
2019-05-09 12:21 ` [PATCH v4 4/8] drm/i915: Shuffle stride checking code around Ville Syrjala
@ 2019-05-09 12:21 ` Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 6/8] drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping Ville Syrjala
` (6 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The display engine stride limits are getting in our way. On SKL+
we are limited to 8k pixels, which is easily exceeded with three
4k displays. To overcome this limitation we can remap the pages
in the GTT to provide the display engine with a view of memory
with a smaller stride.
The code is mostly already there as We already play tricks with
the plane surface address and x/y offsets.
A few caveats apply:
* linear buffers need the fb stride to be page aligned, as
otherwise the remapped lines wouldn't start at the same
spot
* compressed buffers can't be remapped due to the new
ccs hash mode causing the virtual address of the pages
to affect the interpretation of the compressed data. IIRC
the old hash was limited to the low 12 bits so if we were
using that mode we could remap. As it stands we just refuse
to remapp with compressed fbs.
* no remapping gen2/3 as we'd need a fence for the remapped
vma, which we currently don't have. Need to deal with the
fence POT requirements, and do something about the gen2
gtt page size vs tile size difference
v2: Rebase due to is_ccs_modifier()
Fix up the skl+ stride_mult mess
memset() the gtt_view because otherwise we could leave
junk in plane[1] when going from 2 plane to 1 plane format
v3: intel_check_plane_stride() was split out
v4: Drop the aligned viewport stuff, it was meant for ccs which
can't be remapped anyway
v5: Introduce intel_plane_can_remap()
Reorder the code so that plane_state->view gets filled
even for invisible planes, otherwise we'd keep using
stale values and could explode during remapping. The new
logic never remaps invisible planes since we don't have
a viewport, and instead pins the full fb instead
v6: Fix plane src coord checks after remapping by moving
plane_state->base.src to the final plane x/y offsets.
Allow intel_plane_check_stride() to fail even with
remapping (can happen at least with a linear 64bpp
fb with a 4k plane and a suitably inconvenient src
coordinates).
Improve aux plane FIXME (Daniel)
Move some code shuffling into a separate patch (Daniel)
Testcase: igt/kms_big_fb
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 354 ++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_display.h | 2 +
drivers/gpu/drm/i915/intel_sprite.c | 34 ++-
3 files changed, 323 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 321cb6d2bc76..94faac9e3666 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1915,7 +1915,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
- return cpp;
+ return intel_tile_size(dev_priv);
case I915_FORMAT_MOD_X_TILED:
if (IS_GEN(dev_priv, 2))
return 128;
@@ -1958,11 +1958,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 1;
- else
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
}
/* Return the tile dimensions in pixel units */
@@ -2220,16 +2217,8 @@ void intel_add_fb_offsets(int *x, int *y,
int color_plane)
{
- const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
- unsigned int rotation = state->base.rotation;
-
- if (drm_rotation_90_or_270(rotation)) {
- *x += intel_fb->rotated[color_plane].x;
- *y += intel_fb->rotated[color_plane].y;
- } else {
- *x += intel_fb->normal[color_plane].x;
- *y += intel_fb->normal[color_plane].y;
- }
+ *x += state->color_plane[color_plane].x;
+ *y += state->color_plane[color_plane].y;
}
static u32 intel_adjust_tile_offset(int *x, int *y,
@@ -2510,8 +2499,8 @@ bool is_ccs_modifier(u64 modifier)
}
static
-u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
- u32 pixel_format, u64 modifier)
+u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
{
struct intel_crtc *crtc;
struct intel_plane *plane;
@@ -2527,13 +2516,102 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
DRM_MODE_ROTATE_0);
}
+static
+u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+}
+
static u32
intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 64;
- else
+ struct drm_i915_private *dev_priv = to_i915(fb->dev);
+
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ u32 max_stride = intel_plane_fb_max_stride(dev_priv,
+ fb->format->format,
+ fb->modifier);
+
+ /*
+ * To make remapping with linear generally feasible
+ * we need the stride to be page aligned.
+ */
+ if (fb->pitches[color_plane] > max_stride)
+ return intel_tile_size(dev_priv);
+ else
+ return 64;
+ } else {
return intel_tile_width_bytes(fb, color_plane);
+ }
+}
+
+bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ int i;
+
+ /* We don't want to deal with remapping with cursors */
+ if (plane->id == PLANE_CURSOR)
+ return false;
+
+ /*
+ * The display engine limits already match/exceed the
+ * render engine limits, so not much point in remapping.
+ * Would also need to deal with the fence POT alignment
+ * and gen2 2KiB GTT tile size.
+ */
+ if (INTEL_GEN(dev_priv) < 4)
+ return false;
+
+ /*
+ * The new CCS hash mode isn't compatible with remapping as
+ * the virtual address of the pages affects the compressed data.
+ */
+ if (is_ccs_modifier(fb->modifier))
+ return false;
+
+ /* Linear needs a page aligned stride for remapping */
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ unsigned int alignment = intel_tile_size(dev_priv) - 1;
+
+ for (i = 0; i < fb->format->num_planes; i++) {
+ if (fb->pitches[i] & alignment)
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
+ u32 stride, max_stride;
+
+ /*
+ * No remapping for invisible planes since we don't have
+ * an actual source viewport to remap.
+ */
+ if (!plane_state->base.visible)
+ return false;
+
+ if (!intel_plane_can_remap(plane_state))
+ return false;
+
+ /*
+ * FIXME: aux plane limits on gen9+ are
+ * unclear in Bspec, for now no checking.
+ */
+ stride = intel_fb_pitch(fb, 0, rotation);
+ max_stride = plane->max_stride(plane, fb->format->format,
+ fb->modifier, rotation);
+
+ return stride > max_stride;
}
static int
@@ -2701,6 +2779,168 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
return 0;
}
+static void
+intel_plane_remap_gtt(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ struct intel_rotation_info *info = &plane_state->view.rotated;
+ unsigned int rotation = plane_state->base.rotation;
+ int i, num_planes = fb->format->num_planes;
+ unsigned int tile_size = intel_tile_size(dev_priv);
+ unsigned int src_x, src_y;
+ unsigned int src_w, src_h;
+ u32 gtt_offset = 0;
+
+ memset(&plane_state->view, 0, sizeof(plane_state->view));
+ plane_state->view.type = drm_rotation_90_or_270(rotation) ?
+ I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
+
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
+ src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ src_h = drm_rect_height(&plane_state->base.src) >> 16;
+
+ WARN_ON(is_ccs_modifier(fb->modifier));
+
+ /* Make src coordinates relative to the viewport */
+ drm_rect_translate(&plane_state->base.src,
+ -(src_x << 16), -(src_y << 16));
+
+ /* Rotate src coordinates to match rotated GTT view */
+ if (drm_rotation_90_or_270(rotation))
+ drm_rect_rotate(&plane_state->base.src,
+ src_w << 16, src_h << 16,
+ DRM_MODE_ROTATE_270);
+
+ for (i = 0; i < num_planes; i++) {
+ unsigned int hsub = i ? fb->format->hsub : 1;
+ unsigned int vsub = i ? fb->format->vsub : 1;
+ unsigned int cpp = fb->format->cpp[i];
+ unsigned int tile_width, tile_height;
+ unsigned int width, height;
+ unsigned int pitch_tiles;
+ unsigned int x, y;
+ u32 offset;
+
+ intel_tile_dims(fb, i, &tile_width, &tile_height);
+
+ x = src_x / hsub;
+ y = src_y / vsub;
+ width = src_w / hsub;
+ height = src_h / vsub;
+
+ /*
+ * First pixel of the src viewport from the
+ * start of the normal gtt mapping.
+ */
+ x += intel_fb->normal[i].x;
+ y += intel_fb->normal[i].y;
+
+ offset = intel_compute_aligned_offset(dev_priv, &x, &y,
+ fb, i, fb->pitches[i],
+ DRM_MODE_ROTATE_0, tile_size);
+ offset /= tile_size;
+
+ info->plane[i].offset = offset;
+ info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
+ tile_width * cpp);
+ info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
+ info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
+
+ if (drm_rotation_90_or_270(rotation)) {
+ struct drm_rect r;
+
+ /* rotate the x/y offsets to match the GTT view */
+ r.x1 = x;
+ r.y1 = y;
+ r.x2 = x + width;
+ r.y2 = y + height;
+ drm_rect_rotate(&r,
+ info->plane[i].width * tile_width,
+ info->plane[i].height * tile_height,
+ DRM_MODE_ROTATE_270);
+ x = r.x1;
+ y = r.y1;
+
+ pitch_tiles = info->plane[i].height;
+ plane_state->color_plane[i].stride = pitch_tiles * tile_height;
+
+ /* rotate the tile dimensions to match the GTT view */
+ swap(tile_width, tile_height);
+ } else {
+ pitch_tiles = info->plane[i].width;
+ plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
+ }
+
+ /*
+ * We only keep the x/y offsets, so push all of the
+ * gtt offset into the x/y offsets.
+ */
+ intel_adjust_tile_offset(&x, &y,
+ tile_width, tile_height,
+ tile_size, pitch_tiles,
+ gtt_offset * tile_size, 0);
+
+ gtt_offset += info->plane[i].width * info->plane[i].height;
+
+ plane_state->color_plane[i].offset = 0;
+ plane_state->color_plane[i].x = x;
+ plane_state->color_plane[i].y = y;
+ }
+}
+
+static int
+intel_plane_compute_gtt(struct intel_plane_state *plane_state)
+{
+ const struct intel_framebuffer *fb =
+ to_intel_framebuffer(plane_state->base.fb);
+ unsigned int rotation = plane_state->base.rotation;
+ int i, num_planes;
+
+ if (!fb)
+ return 0;
+
+ num_planes = fb->base.format->num_planes;
+
+ if (intel_plane_needs_remap(plane_state)) {
+ intel_plane_remap_gtt(plane_state);
+
+ /*
+ * Sometimes even remapping can't overcome
+ * the stride limitations :( Can happen with
+ * big plane sizes and suitably misaligned
+ * offsets.
+ */
+ return intel_plane_check_stride(plane_state);
+ }
+
+ intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
+
+ for (i = 0; i < num_planes; i++) {
+ plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
+ plane_state->color_plane[i].offset = 0;
+
+ if (drm_rotation_90_or_270(rotation)) {
+ plane_state->color_plane[i].x = fb->rotated[i].x;
+ plane_state->color_plane[i].y = fb->rotated[i].y;
+ } else {
+ plane_state->color_plane[i].x = fb->normal[i].x;
+ plane_state->color_plane[i].y = fb->normal[i].y;
+ }
+ }
+
+ /* Rotate src coordinates to match rotated GTT view */
+ if (drm_rotation_90_or_270(rotation))
+ drm_rect_rotate(&plane_state->base.src,
+ fb->base.width << 16, fb->base.height << 16,
+ DRM_MODE_ROTATE_270);
+
+ return intel_plane_check_stride(plane_state);
+}
+
static int i9xx_format_to_fourcc(int format)
{
switch (format) {
@@ -3199,6 +3439,14 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
plane_state->color_plane[0].x = x;
plane_state->color_plane[0].y = y;
+ /*
+ * Put the final coordinates back so that the src
+ * coordinate checks will see the right values.
+ */
+ drm_rect_translate(&plane_state->base.src,
+ (x << 16) - plane_state->base.src.x1,
+ (y << 16) - plane_state->base.src.y1);
+
return 0;
}
@@ -3255,26 +3503,15 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
- plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
if (!plane_state->base.visible)
return 0;
- /* Rotate src coordinates to match rotated GTT view */
- if (drm_rotation_90_or_270(rotation))
- drm_rect_rotate(&plane_state->base.src,
- fb->width << 16, fb->height << 16,
- DRM_MODE_ROTATE_270);
-
/*
* Handle the AUX surface first since
* the main surface setup depends on it.
@@ -3404,20 +3641,20 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
- int src_x = plane_state->base.src.x1 >> 16;
- int src_y = plane_state->base.src.y1 >> 16;
+ int src_x, src_y;
u32 offset;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
+ if (!plane_state->base.visible)
+ return 0;
+
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
+
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
@@ -3426,8 +3663,17 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
else
offset = 0;
+ /*
+ * Put the final coordinates back so that the src
+ * coordinate checks will see the right values.
+ */
+ drm_rect_translate(&plane_state->base.src,
+ (src_x << 16) - plane_state->base.src.x1,
+ (src_y << 16) - plane_state->base.src.y1);
+
/* HSW/BDW do this automagically in hardware */
if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
+ unsigned int rotation = plane_state->base.rotation;
int src_w = drm_rect_width(&plane_state->base.src) >> 16;
int src_h = drm_rect_height(&plane_state->base.src) >> 16;
@@ -3464,6 +3710,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -3471,10 +3721,6 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = i9xx_check_plane_surface(plane_state);
- if (ret)
- return ret;
-
plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
return 0;
@@ -10001,19 +10247,17 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
int src_x, src_y;
u32 offset;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
-
- ret = intel_plane_check_stride(plane_state);
+ ret = intel_plane_compute_gtt(plane_state);
if (ret)
return ret;
+ if (!plane_state->base.visible)
+ return 0;
+
src_x = plane_state->base.src_x >> 16;
src_y = plane_state->base.src_y >> 16;
@@ -10050,6 +10294,10 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = intel_cursor_check_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -10057,10 +10305,6 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = intel_cursor_check_surface(plane_state);
- if (ret)
- return ret;
-
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 1b6f5a71184d..500eec90928d 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -29,6 +29,7 @@
#include <drm/i915_drm.h>
struct drm_i915_private;
+struct intel_plane_state;
enum i915_gpio {
GPIOA,
@@ -435,5 +436,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
bool constant_n);
bool is_ccs_modifier(u64 modifier);
void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
+bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
#endif
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2913e89280d7..91b461be70be 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -256,6 +256,16 @@ int intel_plane_check_stride(const struct intel_plane_state *plane_state)
unsigned int rotation = plane_state->base.rotation;
u32 stride, max_stride;
+ /*
+ * We ignore stride for all invisible planes that
+ * can be remapped. Otherwise we could end up
+ * with a false positive when the remapping didn't
+ * kick in due the plane being invisible.
+ */
+ if (intel_plane_can_remap(plane_state) &&
+ !plane_state->base.visible)
+ return 0;
+
/* FIXME other color planes? */
stride = plane_state->color_plane[0].stride;
max_stride = plane->max_stride(plane, fb->format->format,
@@ -1417,6 +1427,10 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -1428,10 +1442,6 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = i9xx_check_plane_surface(plane_state);
- if (ret)
- return ret;
-
if (INTEL_GEN(dev_priv) >= 7)
plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
else
@@ -1475,6 +1485,10 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -1482,10 +1496,6 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = i9xx_check_plane_surface(plane_state);
- if (ret)
- return ret;
-
plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
return 0;
@@ -1639,6 +1649,10 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
+ ret = skl_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
if (!plane_state->base.visible)
return 0;
@@ -1654,10 +1668,6 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- ret = skl_check_plane_surface(plane_state);
- if (ret)
- return ret;
-
/* HW only has 8 bits pixel precision, disable plane if invisible */
if (!(plane_state->base.alpha >> 8))
plane_state->base.visible = false;
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 6/8] drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (4 preceding siblings ...)
2019-05-09 12:21 ` [PATCH v4 5/8] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
@ 2019-05-09 12:21 ` Ville Syrjala
2019-05-10 8:40 ` Daniel Vetter
2019-05-09 12:21 ` [PATCH v4 7/8] drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for gen7+ Ville Syrjala
` (5 subsequent siblings)
11 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Align dumb buffer stride to 4k if the fb will be big enough to
require gtt remapping.
v2: Leave the stride alone for buffers that look to be for the cursor
v3: Make it not a hack (Daniel)
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 26 +++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 1 -
drivers/gpu/drm/i915/intel_display.h | 2 ++
3 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4e474bcf4c22..7cafd5612f71 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -52,6 +52,7 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "intel_display.h"
#include "intel_drv.h"
#include "intel_frontbuffer.h"
#include "intel_pm.h"
@@ -560,8 +561,31 @@ i915_gem_dumb_create(struct drm_file *file,
struct drm_device *dev,
struct drm_mode_create_dumb *args)
{
+ int cpp = DIV_ROUND_UP(args->bpp, 8);
+ u32 format;
+
+ switch (cpp) {
+ case 1:
+ format = DRM_FORMAT_C8;
+ break;
+ case 2:
+ format = DRM_FORMAT_RGB565;
+ break;
+ case 4:
+ format = DRM_FORMAT_XRGB8888;
+ break;
+ default:
+ return -EINVAL;
+ }
+
/* have to work out size/pitch and return them */
- args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
+ args->pitch = ALIGN(args->width * cpp, 64);
+
+ /* align stride to page size so that we can remap */
+ if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
+ DRM_FORMAT_MOD_LINEAR))
+ args->pitch = ALIGN(args->pitch, 4096);
+
args->size = args->pitch * args->height;
return i915_gem_create(file, to_i915(dev),
&args->size, &args->handle);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 94faac9e3666..fa317c40d548 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2498,7 +2498,6 @@ bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
-static
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 500eec90928d..1e6533fbd061 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -436,6 +436,8 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
bool constant_n);
bool is_ccs_modifier(u64 modifier);
void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
+u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier);
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
#endif
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 7/8] drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for gen7+
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (5 preceding siblings ...)
2019-05-09 12:21 ` [PATCH v4 6/8] drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping Ville Syrjala
@ 2019-05-09 12:21 ` Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 8/8] drm/i915: Bump gen7+ fb size limits to 16kx16k Ville Syrjala
` (4 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just pick the limit to match the render
engine max stride (256KiB on gen7+, 128KiB on gen4+).
No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
remapping on gen2/3 due extra complications from fence alignment
and gen2 2KiB GTT tile size. Also no real benefit since the
display engine limits already match the other limits.
v2: Rebase due to is_ccs_modifier()
v3: Tweak the comment and commit msg
v4: Fix gen4+ stride limit to be 128KiB
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> #v3
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fa317c40d548..a2e4ef938d53 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2519,6 +2519,19 @@ static
u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
+ /*
+ * Arbitrary limit for gen4+ chosen to match the
+ * render engine max stride.
+ *
+ * The new CCS hash mode makes remapping impossible
+ */
+ if (!is_ccs_modifier(modifier)) {
+ if (INTEL_GEN(dev_priv) >= 7)
+ return 256*1024;
+ else if (INTEL_GEN(dev_priv) >= 4)
+ return 128*1024;
+ }
+
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v4 8/8] drm/i915: Bump gen7+ fb size limits to 16kx16k
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (6 preceding siblings ...)
2019-05-09 12:21 ` [PATCH v4 7/8] drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for gen7+ Ville Syrjala
@ 2019-05-09 12:21 ` Ville Syrjala
2019-05-16 16:33 ` Maarten Lankhorst
2019-05-09 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display Patchwork
` (3 subsequent siblings)
11 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjala @ 2019-05-09 12:21 UTC (permalink / raw)
To: intel-gfx; +Cc: Daniel Vetter
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
With gtt remapping in place we can use arbitrarily large
framebuffers. Let's bump the limits to 16kx16k on gen7+.
The limit was chosen to match the maximum 2D surface size
of the 3D engine.
With the remapping we could easily go higher than that for the
display engine. However the modesetting ddx will blindly assume
it can handle whatever is reported via kms. The oversized
buffer dimensions are not caught by glamor nor Mesa until
finally an assert will trip when genxml attempts to pack the
SURFACE_STATE. So we pick a safe limit to avoid the X server
from crashing (or potentially misbehaving if the genxml asserts
are compiled out).
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110187
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a2e4ef938d53..a495fd2dcaa3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15783,16 +15783,22 @@ int intel_modeset_init(struct drm_device *dev)
}
}
- /* maximum framebuffer dimensions */
- if (IS_GEN(dev_priv, 2)) {
- dev->mode_config.max_width = 2048;
- dev->mode_config.max_height = 2048;
+ /*
+ * Maximum framebuffer dimensions, chosen to match
+ * the maximum render engine surface size on gen4+.
+ */
+ if (INTEL_GEN(dev_priv) >= 7) {
+ dev->mode_config.max_width = 16384;
+ dev->mode_config.max_height = 16384;
+ } else if (INTEL_GEN(dev_priv) >= 4) {
+ dev->mode_config.max_width = 8192;
+ dev->mode_config.max_height = 8192;
} else if (IS_GEN(dev_priv, 3)) {
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
} else {
- dev->mode_config.max_width = 8192;
- dev->mode_config.max_height = 8192;
+ dev->mode_config.max_width = 2048;
+ dev->mode_config.max_height = 2048;
}
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (7 preceding siblings ...)
2019-05-09 12:21 ` [PATCH v4 8/8] drm/i915: Bump gen7+ fb size limits to 16kx16k Ville Syrjala
@ 2019-05-09 14:54 ` Patchwork
2019-05-09 14:58 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-05-09 14:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/60469/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e1a44e3ca92e drm/i915: Add a new "remapped" gtt_view
-:98: CHECK:LINE_SPACING: Please don't use multiple blank lines
#98: FILE: drivers/gpu/drm/i915/i915_gem.c:5106:
+
+
-:246: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:196:
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 9*sizeof(unsigned int));
^
total: 0 errors, 0 warnings, 2 checks, 286 lines checked
08493348be9d drm/i915/selftests: Add mock selftest for remapped vmas
-:76: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#76: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:436:
+ if (left < PAGE_SIZE || left & (PAGE_SIZE-1)) {
^
-:92: CHECK:LINE_SPACING: Please don't use multiple blank lines
#92: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:452:
+
+
-:128: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 8)
#128: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:506:
+ for (t = types; *t; t++) {
for (a = planes; a->width; a++) {
-:172: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#172: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:576:
+ if (view.type == I915_GGTT_VIEW_ROTATED)
-:173: WARNING:LONG_LINE: line over 100 characters
#173: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:577:
+ sg = assert_rotated(obj, &view.rotated, n, sg);
-:174: WARNING:DEEP_INDENTATION: Too many leading tabs - consider code refactoring
#174: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:578:
+ else
-:175: WARNING:LONG_LINE: line over 100 characters
#175: FILE: drivers/gpu/drm/i915/selftests/i915_vma.c:579:
+ sg = assert_remapped(obj, &view.remapped, n, sg);
total: 0 errors, 5 warnings, 2 checks, 165 lines checked
86cfa7fe1e0b drm/i915/selftests: Add live vma selftest
5f08f33bb992 drm/i915: Shuffle stride checking code around
f7bb2263cd69 drm/i915: Overcome display engine stride limits via GTT remapping
494ec5d13440 drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping
5fc14462b19b drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for gen7+
-:44: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#44: FILE: drivers/gpu/drm/i915/intel_display.c:2530:
+ return 256*1024;
^
-:46: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#46: FILE: drivers/gpu/drm/i915/intel_display.c:2532:
+ return 128*1024;
^
total: 0 errors, 0 warnings, 2 checks, 19 lines checked
853938b87ba6 drm/i915: Bump gen7+ fb size limits to 16kx16k
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: GTT remapping for display
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (8 preceding siblings ...)
2019-05-09 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display Patchwork
@ 2019-05-09 14:58 ` Patchwork
2019-05-09 15:14 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-09 23:36 ` ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-05-09 14:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/60469/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add a new "remapped" gtt_view
+drivers/gpu/drm/i915/i915_gem_gtt.c:3633:34: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:3633:34: warning: expression using sizeof(void)
Commit: drm/i915/selftests: Add mock selftest for remapped vmas
Okay!
Commit: drm/i915/selftests: Add live vma selftest
Okay!
Commit: drm/i915: Shuffle stride checking code around
Okay!
Commit: drm/i915: Overcome display engine stride limits via GTT remapping
Okay!
Commit: drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping
Okay!
Commit: drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for gen7+
Okay!
Commit: drm/i915: Bump gen7+ fb size limits to 16kx16k
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: GTT remapping for display
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (9 preceding siblings ...)
2019-05-09 14:58 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-05-09 15:14 ` Patchwork
2019-05-09 23:36 ` ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-05-09 15:14 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/60469/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6072 -> Patchwork_12991
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/
New tests
---------
New tests have been introduced between CI_DRM_6072 and Patchwork_12991:
### New IGT tests (1) ###
* igt@i915_selftest@live_vma:
- Statuses : 41 pass(s)
- Exec time: [0.33, 1.23] s
Known issues
------------
Here are the changes found in Patchwork_12991 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#110235])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-bdw-gvtdvm/igt@i915_selftest@live_contexts.html
* igt@prime_vgem@basic-fence-flip:
- fi-glk-dsi: [PASS][3] -> [SKIP][4] ([fdo#109271])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-glk-dsi/igt@prime_vgem@basic-fence-flip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-glk-dsi/igt@prime_vgem@basic-fence-flip.html
- fi-bxt-dsi: [PASS][5] -> [SKIP][6] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-bxt-dsi/igt@prime_vgem@basic-fence-flip.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-bxt-dsi/igt@prime_vgem@basic-fence-flip.html
- fi-kbl-r: [PASS][7] -> [SKIP][8] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-kbl-r/igt@prime_vgem@basic-fence-flip.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-kbl-r/igt@prime_vgem@basic-fence-flip.html
- fi-skl-6600u: [PASS][9] -> [SKIP][10] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-skl-6600u/igt@prime_vgem@basic-fence-flip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-skl-6600u/igt@prime_vgem@basic-fence-flip.html
- fi-whl-u: [PASS][11] -> [SKIP][12] ([fdo#109271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-whl-u/igt@prime_vgem@basic-fence-flip.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-whl-u/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-7500u: [DMESG-WARN][13] ([fdo#105128] / [fdo#107139]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-kbl-7500u/igt@gem_exec_suspend@basic-s4-devices.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-kbl-7500u/igt@gem_exec_suspend@basic-s4-devices.html
#### Warnings ####
* igt@i915_selftest@live_hangcheck:
- fi-apl-guc: [INCOMPLETE][15] ([fdo#103927] / [fdo#110624]) -> [DMESG-FAIL][16] ([fdo#110620])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-apl-guc/igt@i915_selftest@live_hangcheck.html
* igt@runner@aborted:
- fi-apl-guc: [FAIL][17] ([fdo#110624]) -> [FAIL][18] ([fdo#110622])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/fi-apl-guc/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/fi-apl-guc/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[fdo#110531]: https://bugs.freedesktop.org/show_bug.cgi?id=110531
[fdo#110620]: https://bugs.freedesktop.org/show_bug.cgi?id=110620
[fdo#110622]: https://bugs.freedesktop.org/show_bug.cgi?id=110622
[fdo#110624]: https://bugs.freedesktop.org/show_bug.cgi?id=110624
Participating hosts (49 -> 42)
------------------------------
Additional (1): fi-blb-e6850
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-byt-clapper
Build changes
-------------
* IGT: IGT_4976 -> IGTPW_2953
* Linux: CI_DRM_6072 -> Patchwork_12991
CI_DRM_6072: 645586708589c3d2ac81114595e875cdfbbff385 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2953: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2953/
IGT_4976: b1d91d0228db999145405e529952ca49bab7f706 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12991: 853938b87ba6def92b1f4b21aa62e8e78df5b3c3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
853938b87ba6 drm/i915: Bump gen7+ fb size limits to 16kx16k
5fc14462b19b drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for gen7+
494ec5d13440 drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping
f7bb2263cd69 drm/i915: Overcome display engine stride limits via GTT remapping
5f08f33bb992 drm/i915: Shuffle stride checking code around
86cfa7fe1e0b drm/i915/selftests: Add live vma selftest
08493348be9d drm/i915/selftests: Add mock selftest for remapped vmas
e1a44e3ca92e drm/i915: Add a new "remapped" gtt_view
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: GTT remapping for display
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
` (10 preceding siblings ...)
2019-05-09 15:14 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-05-09 23:36 ` Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2019-05-09 23:36 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/60469/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6072_full -> Patchwork_12991_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12991_full:
### IGT changes ###
#### Possible regressions ####
* {igt@kms_big_fb@x-tiled-32bpp-rotate-90} (NEW):
- shard-iclb: NOTRUN -> [SKIP][1] +33 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-iclb7/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
New tests
---------
New tests have been introduced between CI_DRM_6072_full and Patchwork_12991_full:
### New IGT tests (75) ###
* igt@i915_selftest@live_vma:
- Statuses : 7 pass(s)
- Exec time: [0.33, 1.78] s
* igt@kms_big_fb@linear-16bpp-rotate-0:
- Statuses : 7 pass(s)
- Exec time: [1.57, 5.64] s
* igt@kms_big_fb@linear-16bpp-rotate-180:
- Statuses : 7 pass(s)
- Exec time: [1.55, 5.53] s
* igt@kms_big_fb@linear-16bpp-rotate-270:
- Statuses : 6 skip(s)
- Exec time: [0.29, 1.81] s
* igt@kms_big_fb@linear-16bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.49, 4.00] s
* igt@kms_big_fb@linear-32bpp-rotate-0:
- Statuses : 6 pass(s)
- Exec time: [1.76, 8.58] s
* igt@kms_big_fb@linear-32bpp-rotate-180:
- Statuses : 7 pass(s)
- Exec time: [1.67, 8.21] s
* igt@kms_big_fb@linear-32bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.36, 7.11] s
* igt@kms_big_fb@linear-32bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.33, 6.00] s
* igt@kms_big_fb@linear-64bpp-rotate-0:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 3.44] s
* igt@kms_big_fb@linear-64bpp-rotate-180:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 3.30] s
* igt@kms_big_fb@linear-64bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.0, 1.69] s
* igt@kms_big_fb@linear-64bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.0, 3.96] s
* igt@kms_big_fb@linear-8bpp-rotate-0:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@linear-8bpp-rotate-180:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@linear-8bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@linear-8bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@linear-addfb:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@kms_big_fb@x-tiled-16bpp-rotate-0:
- Statuses : 6 pass(s)
- Exec time: [1.49, 2.49] s
* igt@kms_big_fb@x-tiled-16bpp-rotate-180:
- Statuses : 7 pass(s)
- Exec time: [1.64, 6.71] s
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.20, 3.33] s
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.45, 3.75] s
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- Statuses : 7 pass(s)
- Exec time: [1.70, 8.23] s
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- Statuses : 7 pass(s)
- Exec time: [1.69, 8.33] s
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.30, 5.85] s
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.41, 6.08] s
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 3.13] s
* igt@kms_big_fb@x-tiled-64bpp-rotate-180:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 3.15] s
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.0, 1.76] s
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.0, 1.63] s
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@x-tiled-8bpp-rotate-180:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@x-tiled-addfb:
- Statuses : 7 pass(s)
- Exec time: [0.0, 0.00] s
* igt@kms_big_fb@x-tiled-addfb-size-offset-overflow:
- Statuses : 3 pass(s) 3 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@x-tiled-addfb-size-overflow:
- Statuses : 6 pass(s) 1 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 5.20] s
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 5.18] s
* igt@kms_big_fb@y-tiled-16bpp-rotate-270:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 1.93] s
* igt@kms_big_fb@y-tiled-16bpp-rotate-90:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 3.36] s
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 7.98] s
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 8.13] s
* igt@kms_big_fb@y-tiled-32bpp-rotate-270:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 8.56] s
* igt@kms_big_fb@y-tiled-32bpp-rotate-90:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 8.13] s
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 3.00] s
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 2.99] s
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.0, 1.52] s
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.0, 1.42] s
* igt@kms_big_fb@y-tiled-8bpp-rotate-0:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@y-tiled-addfb:
- Statuses : 4 pass(s) 2 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- Statuses : 3 pass(s) 4 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 5.24] s
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 5.23] s
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 2.87] s
* igt@kms_big_fb@yf-tiled-16bpp-rotate-90:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 1.79] s
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 7.95] s
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- Statuses : 5 pass(s) 1 skip(s)
- Exec time: [0.0, 8.44] s
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 8.09] s
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 7.96] s
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@yf-tiled-8bpp-rotate-180:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- Statuses : 7 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@kms_big_fb@yf-tiled-addfb:
- Statuses : 5 pass(s) 2 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- Statuses : 3 pass(s) 4 skip(s)
- Exec time: [0.0, 0.00] s
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- Statuses : 4 pass(s) 2 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_12991_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_tiled_swapping@non-threaded:
- shard-hsw: [PASS][2] -> [INCOMPLETE][3] ([fdo#103540]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-hsw8/igt@gem_tiled_swapping@non-threaded.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-hsw1/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- shard-skl: [PASS][4] -> [FAIL][5] ([fdo#107931] / [fdo#108303])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl7/igt@kms_flip_tiling@flip-changes-tiling-y.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl8/igt@kms_flip_tiling@flip-changes-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-iclb: [PASS][6] -> [FAIL][7] ([fdo#103167]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-skl: [PASS][8] -> [FAIL][9] ([fdo#103167] / [fdo#110379])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-snb: [PASS][10] -> [DMESG-WARN][11] ([fdo#102365])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-snb2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-snb4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][12] -> [FAIL][13] ([fdo#108145] / [fdo#110403])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][14] -> [FAIL][15] ([fdo#103166])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-x.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109441]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [PASS][18] -> [DMESG-WARN][19] ([fdo#108566]) +4 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-apl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-apl5/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@prime_vgem@basic-fence-flip:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109294])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-iclb1/igt@prime_vgem@basic-fence-flip.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-iclb7/igt@prime_vgem@basic-fence-flip.html
- shard-skl: [PASS][22] -> [SKIP][23] ([fdo#109271])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl8/igt@prime_vgem@basic-fence-flip.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl10/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@i915_suspend@debugfs-reader:
- shard-apl: [DMESG-WARN][24] ([fdo#108566]) -> [PASS][25] +5 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-apl6/igt@i915_suspend@debugfs-reader.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-apl6/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_crc@cursor-256x256-suspend:
- shard-apl: [FAIL][26] ([fdo#103375]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-apl5/igt@kms_cursor_crc@cursor-256x256-suspend.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-apl4/igt@kms_cursor_crc@cursor-256x256-suspend.html
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: [FAIL][28] ([fdo#103232]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-apl5/igt@kms_cursor_crc@cursor-256x85-random.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-apl8/igt@kms_cursor_crc@cursor-256x85-random.html
- shard-skl: [FAIL][30] ([fdo#103232]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl2/igt@kms_cursor_crc@cursor-256x85-random.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl1/igt@kms_cursor_crc@cursor-256x85-random.html
- shard-kbl: [FAIL][32] ([fdo#103232]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-kbl7/igt@kms_cursor_crc@cursor-256x85-random.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-kbl7/igt@kms_cursor_crc@cursor-256x85-random.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-bottom-edge:
- shard-snb: [SKIP][34] ([fdo#109271] / [fdo#109278]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-snb7/igt@kms_cursor_edge_walk@pipe-b-64x64-bottom-edge.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-snb7/igt@kms_cursor_edge_walk@pipe-b-64x64-bottom-edge.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [DMESG-WARN][36] ([fdo#108566]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-kbl1/igt@kms_flip@flip-vs-suspend.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-kbl5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: [FAIL][38] ([fdo#100368]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack:
- shard-skl: [FAIL][40] ([fdo#103167]) -> [PASS][41] +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl5/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl8/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt:
- shard-skl: [FAIL][42] ([fdo#103167] / [fdo#110379]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl5/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl7/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][44] ([fdo#103167]) -> [PASS][45] +5 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][46] ([fdo#108145]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][48] ([fdo#108145] / [fdo#110403]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][50] ([fdo#103166]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-y.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [SKIP][52] ([fdo#109441]) -> [PASS][53] +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-iclb4/igt@kms_psr@psr2_dpms.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-iclb2/igt@kms_psr@psr2_dpms.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][54] ([fdo#99912]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-kbl5/igt@kms_setmode@basic.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-kbl3/igt@kms_setmode@basic.html
* igt@perf@oa-exponents:
- shard-glk: [FAIL][56] ([fdo#105483]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-glk5/igt@perf@oa-exponents.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-glk3/igt@perf@oa-exponents.html
#### Warnings ####
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-skl: [INCOMPLETE][58] ([fdo#107807]) -> [SKIP][59] ([fdo#109271])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6072/shard-skl10/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/shard-skl10/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103375]: https://bugs.freedesktop
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12991/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 4/8] drm/i915: Shuffle stride checking code around
2019-05-09 12:21 ` [PATCH v4 4/8] drm/i915: Shuffle stride checking code around Ville Syrjala
@ 2019-05-10 8:37 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2019-05-10 8:37 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Daniel Vetter, intel-gfx
On Thu, May 09, 2019 at 03:21:55PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reorganize some fb stride checking code a bit to prepare for
> gtt remapping. And do a bit of s/pitch/stride/ renaming in the
> process for a bit more uniformity (apart from the whole
> fb->pitches[] thing).
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 64 ++++++++++++++--------------
> 1 file changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f4e6e9a8bbf9..321cb6d2bc76 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2509,6 +2509,33 @@ bool is_ccs_modifier(u64 modifier)
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
>
> +static
> +u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
> + u32 pixel_format, u64 modifier)
> +{
> + struct intel_crtc *crtc;
> + struct intel_plane *plane;
> +
> + /*
> + * We assume the primary plane for pipe A has
> + * the highest stride limits of them all.
> + */
> + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> + plane = to_intel_plane(crtc->base.primary);
> +
> + return plane->max_stride(plane, pixel_format, modifier,
> + DRM_MODE_ROTATE_0);
> +}
> +
> +static u32
> +intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> +{
> + if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> + return 64;
> + else
> + return intel_tile_width_bytes(fb, color_plane);
> +}
> +
> static int
> intel_fill_fb_info(struct drm_i915_private *dev_priv,
> struct drm_framebuffer *fb)
> @@ -3586,15 +3613,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> return ret;
> }
>
> -static u32
> -intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> -{
> - if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> - return 64;
> - else
> - return intel_tile_width_bytes(fb, color_plane);
> -}
> -
> static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> {
> struct drm_device *dev = intel_crtc->base.dev;
> @@ -14921,31 +14939,13 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> .dirty = intel_user_framebuffer_dirty,
> };
>
> -static
> -u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
> - u32 pixel_format, u64 fb_modifier)
> -{
> - struct intel_crtc *crtc;
> - struct intel_plane *plane;
> -
> - /*
> - * We assume the primary plane for pipe A has
> - * the highest stride limits of them all.
> - */
> - crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> - plane = to_intel_plane(crtc->base.primary);
> -
> - return plane->max_stride(plane, pixel_format, fb_modifier,
> - DRM_MODE_ROTATE_0);
> -}
> -
> static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> struct drm_i915_gem_object *obj,
> struct drm_mode_fb_cmd2 *mode_cmd)
> {
> struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> struct drm_framebuffer *fb = &intel_fb->base;
> - u32 pitch_limit;
> + u32 max_stride;
> unsigned int tiling, stride;
> int ret = -EINVAL;
> int i;
> @@ -14997,13 +14997,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
>
> - pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->pixel_format,
> - mode_cmd->modifier[0]);
> - if (mode_cmd->pitches[0] > pitch_limit) {
> + max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
> + mode_cmd->modifier[0]);
> + if (mode_cmd->pitches[0] > max_stride) {
> DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
> mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
> "tiled" : "linear",
> - mode_cmd->pitches[0], pitch_limit);
> + mode_cmd->pitches[0], max_stride);
> goto err;
> }
>
> --
> 2.21.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 6/8] drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping
2019-05-09 12:21 ` [PATCH v4 6/8] drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping Ville Syrjala
@ 2019-05-10 8:40 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2019-05-10 8:40 UTC (permalink / raw)
To: Ville Syrjala; +Cc: Daniel Vetter, intel-gfx
On Thu, May 09, 2019 at 03:21:57PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Align dumb buffer stride to 4k if the fb will be big enough to
> require gtt remapping.
>
> v2: Leave the stride alone for buffers that look to be for the cursor
> v3: Make it not a hack (Daniel)
>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Yeah I think this is a reasonable heuristics.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 26 +++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_display.c | 1 -
> drivers/gpu/drm/i915/intel_display.h | 2 ++
> 3 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4e474bcf4c22..7cafd5612f71 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -52,6 +52,7 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
>
> +#include "intel_display.h"
> #include "intel_drv.h"
> #include "intel_frontbuffer.h"
> #include "intel_pm.h"
> @@ -560,8 +561,31 @@ i915_gem_dumb_create(struct drm_file *file,
> struct drm_device *dev,
> struct drm_mode_create_dumb *args)
> {
> + int cpp = DIV_ROUND_UP(args->bpp, 8);
> + u32 format;
> +
> + switch (cpp) {
> + case 1:
> + format = DRM_FORMAT_C8;
> + break;
> + case 2:
> + format = DRM_FORMAT_RGB565;
> + break;
> + case 4:
> + format = DRM_FORMAT_XRGB8888;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> /* have to work out size/pitch and return them */
> - args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
> + args->pitch = ALIGN(args->width * cpp, 64);
> +
> + /* align stride to page size so that we can remap */
> + if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format,
> + DRM_FORMAT_MOD_LINEAR))
> + args->pitch = ALIGN(args->pitch, 4096);
> +
> args->size = args->pitch * args->height;
> return i915_gem_create(file, to_i915(dev),
> &args->size, &args->handle);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 94faac9e3666..fa317c40d548 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2498,7 +2498,6 @@ bool is_ccs_modifier(u64 modifier)
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
>
> -static
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier)
> {
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 500eec90928d..1e6533fbd061 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -436,6 +436,8 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
> bool constant_n);
> bool is_ccs_modifier(u64 modifier);
> void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> +u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> + u32 pixel_format, u64 modifier);
> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
>
> #endif
> --
> 2.21.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 8/8] drm/i915: Bump gen7+ fb size limits to 16kx16k
2019-05-09 12:21 ` [PATCH v4 8/8] drm/i915: Bump gen7+ fb size limits to 16kx16k Ville Syrjala
@ 2019-05-16 16:33 ` Maarten Lankhorst
2019-05-20 15:14 ` Ville Syrjälä
0 siblings, 1 reply; 17+ messages in thread
From: Maarten Lankhorst @ 2019-05-16 16:33 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Daniel Vetter
Op 09-05-2019 om 14:21 schreef Ville Syrjala:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> With gtt remapping in place we can use arbitrarily large
> framebuffers. Let's bump the limits to 16kx16k on gen7+.
> The limit was chosen to match the maximum 2D surface size
> of the 3D engine.
>
> With the remapping we could easily go higher than that for the
> display engine. However the modesetting ddx will blindly assume
> it can handle whatever is reported via kms. The oversized
> buffer dimensions are not caught by glamor nor Mesa until
> finally an assert will trip when genxml attempts to pack the
> SURFACE_STATE. So we pick a safe limit to avoid the X server
> from crashing (or potentially misbehaving if the genxml asserts
> are compiled out).
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110187
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a2e4ef938d53..a495fd2dcaa3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15783,16 +15783,22 @@ int intel_modeset_init(struct drm_device *dev)
> }
> }
>
> - /* maximum framebuffer dimensions */
> - if (IS_GEN(dev_priv, 2)) {
> - dev->mode_config.max_width = 2048;
> - dev->mode_config.max_height = 2048;
> + /*
> + * Maximum framebuffer dimensions, chosen to match
> + * the maximum render engine surface size on gen4+.
> + */
> + if (INTEL_GEN(dev_priv) >= 7) {
> + dev->mode_config.max_width = 16384;
> + dev->mode_config.max_height = 16384;
> + } else if (INTEL_GEN(dev_priv) >= 4) {
> + dev->mode_config.max_width = 8192;
> + dev->mode_config.max_height = 8192;
> } else if (IS_GEN(dev_priv, 3)) {
> dev->mode_config.max_width = 4096;
> dev->mode_config.max_height = 4096;
> } else {
> - dev->mode_config.max_width = 8192;
> - dev->mode_config.max_height = 8192;
> + dev->mode_config.max_width = 2048;
> + dev->mode_config.max_height = 2048;
> }
>
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
Should be good enough, lets not go too crazy. :)
For whole series:
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v4 8/8] drm/i915: Bump gen7+ fb size limits to 16kx16k
2019-05-16 16:33 ` Maarten Lankhorst
@ 2019-05-20 15:14 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2019-05-20 15:14 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: Daniel Vetter, intel-gfx
On Thu, May 16, 2019 at 06:33:21PM +0200, Maarten Lankhorst wrote:
> Op 09-05-2019 om 14:21 schreef Ville Syrjala:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > With gtt remapping in place we can use arbitrarily large
> > framebuffers. Let's bump the limits to 16kx16k on gen7+.
> > The limit was chosen to match the maximum 2D surface size
> > of the 3D engine.
> >
> > With the remapping we could easily go higher than that for the
> > display engine. However the modesetting ddx will blindly assume
> > it can handle whatever is reported via kms. The oversized
> > buffer dimensions are not caught by glamor nor Mesa until
> > finally an assert will trip when genxml attempts to pack the
> > SURFACE_STATE. So we pick a safe limit to avoid the X server
> > from crashing (or potentially misbehaving if the genxml asserts
> > are compiled out).
> >
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110187
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
> > 1 file changed, 12 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a2e4ef938d53..a495fd2dcaa3 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15783,16 +15783,22 @@ int intel_modeset_init(struct drm_device *dev)
> > }
> > }
> >
> > - /* maximum framebuffer dimensions */
> > - if (IS_GEN(dev_priv, 2)) {
> > - dev->mode_config.max_width = 2048;
> > - dev->mode_config.max_height = 2048;
> > + /*
> > + * Maximum framebuffer dimensions, chosen to match
> > + * the maximum render engine surface size on gen4+.
> > + */
> > + if (INTEL_GEN(dev_priv) >= 7) {
> > + dev->mode_config.max_width = 16384;
> > + dev->mode_config.max_height = 16384;
> > + } else if (INTEL_GEN(dev_priv) >= 4) {
> > + dev->mode_config.max_width = 8192;
> > + dev->mode_config.max_height = 8192;
> > } else if (IS_GEN(dev_priv, 3)) {
> > dev->mode_config.max_width = 4096;
> > dev->mode_config.max_height = 4096;
> > } else {
> > - dev->mode_config.max_width = 8192;
> > - dev->mode_config.max_height = 8192;
> > + dev->mode_config.max_width = 2048;
> > + dev->mode_config.max_height = 2048;
> > }
> >
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
>
> Should be good enough, lets not go too crazy. :)
>
> For whole series:
>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Yay! Everything rb'd so series pushed to dinq.
Thanks for the reviews everyone.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2019-05-20 15:14 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-05-09 12:21 [PATCH v4 0/8] drm/i915: GTT remapping for display Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 1/8] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 2/8] drm/i915/selftests: Add mock selftest for remapped vmas Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 3/8] drm/i915/selftests: Add live vma selftest Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 4/8] drm/i915: Shuffle stride checking code around Ville Syrjala
2019-05-10 8:37 ` Daniel Vetter
2019-05-09 12:21 ` [PATCH v4 5/8] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 6/8] drm/i915: Align dumb buffer stride to 4k to allow for gtt remapping Ville Syrjala
2019-05-10 8:40 ` Daniel Vetter
2019-05-09 12:21 ` [PATCH v4 7/8] drm/i915: Bump fb stride limit to 128KiB for gen4+ and 256KiB for gen7+ Ville Syrjala
2019-05-09 12:21 ` [PATCH v4 8/8] drm/i915: Bump gen7+ fb size limits to 16kx16k Ville Syrjala
2019-05-16 16:33 ` Maarten Lankhorst
2019-05-20 15:14 ` Ville Syrjälä
2019-05-09 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display Patchwork
2019-05-09 14:58 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-05-09 15:14 ` ✓ Fi.CI.BAT: success " Patchwork
2019-05-09 23:36 ` ✓ Fi.CI.IGT: " Patchwork
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