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[174.21.72.39]) by smtp.gmail.com with ESMTPSA id a10sm14065691pfg.20.2021.08.31.10.59.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Aug 2021 10:59:16 -0700 (PDT) Subject: Re: [PATCH v2 04/19] host-utils: add 128-bit quotient support to divu128/divs128 To: Luis Pires , qemu-devel@nongnu.org, qemu-ppc@nongnu.org References: <20210831164007.297781-1-luis.pires@eldorado.org.br> <20210831164007.297781-5-luis.pires@eldorado.org.br> From: Richard Henderson Message-ID: Date: Tue, 31 Aug 2021 10:59:14 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210831164007.297781-5-luis.pires@eldorado.org.br> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.932, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: groug@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/31/21 9:39 AM, Luis Pires wrote: > These will be used to implement new decimal floating point > instructions from Power ISA 3.1. > > A new argument, prem, was added to divu128/divs128 to receive the > remainder, freeing up phigh to receive the high 64 bits of the > quotient. > > For scenarios supported by the previous implementation > (<= 64-bit quotient) with large (> 64-bit) dividends, testing showed > that: > - when dividend >> divisor, the performance of the new implementation > is equivalent to the old one. > - as the dividend and the divisor get closer (e.g. 65-bit dividend and > 64-bit divisor), the performance is significantly improved, due to the > smaller number of shift-subtract iterations. Hmm. I'll note that we have a better divmod primitive in tree, but we aren't using it here: udiv_qrnnd in include/fpu/softfloat-macros.h. Given that none of the existing uses require the high part, should we be creating a new interface? The bug you highlight wrt truncation could be fixed separately. > -void divs128(int64_t *plow, int64_t *phigh, int64_t divisor) > +void divs128(uint64_t *plow, int64_t *phigh, int64_t *prem, int64_t divisor) > { > - int sgn_dvdnd = *phigh < 0; > - int sgn_divsr = divisor < 0; > + int neg_quotient = 0, neg_remainder = 0; You might as well use bool. r~