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Tue, 2 Jun 2020 22:12:12 +0000 Subject: RE: [PATCH] x86/resctrl: Fix memory bandwidth counter width for AMD To: Reinette Chatre , "fenghua.yu@intel.com" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "x86@kernel.org" , "hpa@zytor.com" , "linux-kernel@vger.kernel.org" References: <159105232628.48268.7763865625735367523.stgit@naples-babu.amd.com> From: Babu Moger Message-ID: Date: Tue, 2 Jun 2020 17:12:11 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SN4PR0701CA0017.namprd07.prod.outlook.com (2603:10b6:803:28::27) To SN1PR12MB2560.namprd12.prod.outlook.com (2603:10b6:802:26::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [10.236.31.79] (165.204.77.1) by SN4PR0701CA0017.namprd07.prod.outlook.com (2603:10b6:803:28::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: BAio/9qEKvuqqgjiNtCnpwcgm4qAXzGIijZ6cCjbSdF4PAE4umOcl+6HLM2eIh4lxoD9cxRwNnPzNoKXsruZOdOzT1DGgurVXwroVolB+UFMwnlyTuCsPaAGKesGBKDtXm6S09N1IRrpALYJzKGoe4Gbw6/zqfqJaVWdNl1XmTjNZtWD2iuc/FGf7XV5rtfV5i51mfK9NZgF8eHPNumV4KK0xAqyoJMEKl+/LjUABVr1E/6998iYUaZLPYmkCdzChNJtCywrPmtygP3gwTZ+jrHiYTJ7R6erX3X3K4iWLMMFMb/QR9JGyjf7qRwHWZjbEgmq/aQi7SDAGJyx8g0URH+4BO+9riCyWriR2iihXmqgXaFnwtUCwiS6TYM/kZXHKjKOLMQCKJ6re5cNJ7ZtAE3Gptgl/uoUMhfoDXPJD/86qPHRPwneVNv1tv8mYdILD6xE0CnvqFsDbRWY6ITYoMP8tnUE4Gucg9cbt1y7RzE= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7816d29-2615-4579-b927-08d807420010 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2020 22:12:12.4666 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Fkgg208uD4KtGtPRTqTgZ5Tk3a7quR60mFiYFFRfmcKr6gRmqWtKDFs0jcmpZoRU X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2463 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Reinette Chatre > Sent: Tuesday, June 2, 2020 4:51 PM > To: Moger, Babu ; fenghua.yu@intel.com; > tglx@linutronix.de; mingo@redhat.com; bp@alien8.de; x86@kernel.org; > hpa@zytor.com; linux-kernel@vger.kernel.org > Subject: Re: [PATCH] x86/resctrl: Fix memory bandwidth counter width for AMD > > Hi Babu, > > On 6/1/2020 4:00 PM, Babu Moger wrote: > > Memory bandwidth is calculated reading the monitoring counter > > at two intervals and calculating the delta. It is the software’s > > responsibility to read the count often enough to avoid having > > the count roll over _twice_ between reads. > > > > The current code hardcodes the bandwidth monitoring counter's width > > to 24 bits for AMD. This is due to default base counter width which > > is 24. Currently, AMD does not implement the CPUID 0xF.[ECX=1]:EAX > > to adjust the counter width. But, the AMD hardware supports much > > wider bandwidth counter with the default width of 44 bits. > > > > Kernel reads these monitoring counters every 1 second and adjusts the > > counter value for overflow. With 24 bits and scale value of 64 for AMD, > > it can only measure up to 1GB/s without overflowing. For the rates > > above 1GB/s this will fail to measure the bandwidth. > > > > Fix the issue setting the default width to 44 bits by adjusting the > > offset. > > > > AMD future products will implement the CPUID 0xF.[ECX=1]:EAX. > > > > Signed-off-by: Babu Moger > > --- > > - Sending it second time. Email client had some issues first time. > > - Generated the patch on top of > > git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git (x86/cache). > > > > arch/x86/kernel/cpu/resctrl/core.c | 8 +++++++- > > arch/x86/kernel/cpu/resctrl/internal.h | 1 + > > 2 files changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/kernel/cpu/resctrl/core.c > b/arch/x86/kernel/cpu/resctrl/core.c > > index 12f967c6b603..6040e9ae541b 100644 > > --- a/arch/x86/kernel/cpu/resctrl/core.c > > +++ b/arch/x86/kernel/cpu/resctrl/core.c > > @@ -983,7 +983,13 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) > > c->x86_cache_occ_scale = ebx; > > if (c->x86_vendor == X86_VENDOR_INTEL) > > c->x86_cache_mbm_width_offset = eax & 0xff; > > - else > > + else if (c->x86_vendor == X86_VENDOR_AMD) { > > + if (eax) > > This test checks if _any_ bit is set in eax ... > > > + c->x86_cache_mbm_width_offset = eax & 0xff; > > ... with the assumption that the first eight bits contain a value. > > Even so, now that Intel and AMD will be using eax in the same way, > perhaps it can be done simpler by always using eax to obtain the offset > (and thus avoid the code duplication) and on AMD initialize the default > if it cannot be obtained from eax? > > What I mean is something like: > > @@ -1024,10 +1024,12 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) > > c->x86_cache_max_rmid = ecx; > c->x86_cache_occ_scale = ebx; > - if (c->x86_vendor == X86_VENDOR_INTEL) > - c->x86_cache_mbm_width_offset = eax & 0xff; > - else > - c->x86_cache_mbm_width_offset = -1; > + c->x86_cache_mbm_width_offset = eax & 0xff; > + if (c->x86_vendor == X86_VENDOR_AMD && > + c->x86_cache_mbm_width_offset == 0) { > + c->x86_cache_mbm_width_offset = > + MBM_CNTR_WIDTH_OFFSET_AMD; > + } > } > } > > What do you think? That looks good. But we still need to keep the default(c->x86_cache_mbm_width_offset = -1;) for non-AMD and non-Intel. How about this? diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 12f967c6b603..7269bd896ba9 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -983,6 +983,9 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) c->x86_cache_occ_scale = ebx; if (c->x86_vendor == X86_VENDOR_INTEL) c->x86_cache_mbm_width_offset = eax & 0xff; + else if (c->x86_vendor == X86_VENDOR_AMD) + c->x86_cache_mbm_width_offset = eax ? eax & 0xff : + MBM_CNTR_WIDTH_OFFSET_AMD; else c->x86_cache_mbm_width_offset = -1; }