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From: Nirmoy <nirmodas@amd.com>
To: Evan Quan <evan.quan@amd.com>, amd-gfx@lists.freedesktop.org
Cc: alexander.deucher@amd.com
Subject: Re: [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature
Date: Wed, 12 Aug 2020 08:09:17 +0200	[thread overview]
Message-ID: <c7c65f6c-aca0-be33-7f73-23c172bb565e@amd.com> (raw)
In-Reply-To: <20200812045647.20541-3-evan.quan@amd.com>


On 8/12/20 6:56 AM, Evan Quan wrote:
> Support Navi1X mgpu fan boost enablement.
>
> Change-Id: Iafbf07c56462120d2db578b6af45dd7f985a4cc1
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>   .../drm/amd/powerplay/inc/smu_v11_0_ppsmc.h   |  4 +++-
>   drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 21 +++++++++++++++++++
>   2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> index 406bfd187ce8..fa0174dc7e0e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_ppsmc.h
> @@ -123,7 +123,9 @@
>   #define PPSMC_MSG_DALDisableDummyPstateChange    0x49
>   #define PPSMC_MSG_DALEnableDummyPstateChange     0x4A
>   
> -#define PPSMC_Message_Count                      0x4B
> +#define PPSMC_MSG_SetMGpuFanBoostLimitRpm        0x4C
> +
> +#define PPSMC_Message_Count                      0x4D
>   
>   typedef uint32_t PPSMC_Result;
>   typedef uint32_t PPSMC_Msg;
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 61e2971be9f3..a86cd819b44b 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -138,6 +138,7 @@ static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
>   	MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE,	PPSMC_MSG_DALEnableDummyPstateChange,	0),
>   	MSG_MAP(GetVoltageByDpm,		PPSMC_MSG_GetVoltageByDpm,		0),
>   	MSG_MAP(GetVoltageByDpmOverdrive,	PPSMC_MSG_GetVoltageByDpmOverdrive,	0),
> +	MSG_MAP(SetMGpuFanBoostLimitRpm,	PPSMC_MSG_SetMGpuFanBoostLimitRpm,	0),
>   };
>   
>   static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
> @@ -2555,6 +2556,25 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
>   	return sizeof(struct gpu_metrics_v1_0);
>   }
>   
> +static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> +{
> +	struct amdgpu_device *adev = smu->adev;
> +	uint32_t param = 0;
> +
> +	/* Navi12 does not support this */
> +	if (adev->asic_type == CHIP_NAVI12)
> +		return 0;
> +
> +	if (adev->pdev->device == 0x7312 &&
> +	    adev->external_rev_id == 0)
> +		param = 0xD188;


Can you please add a comment explaining above condition?

Apart from that, the series is Acked-by: Nirmoy Das <nirmoy.das@amd.com>


> +
> +	return smu_cmn_send_smc_msg_with_param(smu,
> +					       SMU_MSG_SetMGpuFanBoostLimitRpm,
> +					       param,
> +					       NULL);
> +}
> +
>   static const struct pptable_funcs navi10_ppt_funcs = {
>   	.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
>   	.set_default_dpm_table = navi10_set_default_dpm_table,
> @@ -2636,6 +2656,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
>   	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
>   	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
>   	.get_gpu_metrics = navi10_get_gpu_metrics,
> +	.enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
>   };
>   
>   void navi10_set_ppt_funcs(struct smu_context *smu)
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  reply	other threads:[~2020-08-12  6:05 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-12  4:56 [PATCH 1/4] drm/amd/powerplay: optimize the interface for mgpu fan boost enablement Evan Quan
2020-08-12  4:56 ` [PATCH 2/4] drm/amd/powerplay: enable swSMU mgpu fan boost support Evan Quan
2020-08-12  4:56 ` [PATCH 3/4] drm/amd/powerplay: enable Navi1X mgpu fan boost feature Evan Quan
2020-08-12  6:09   ` Nirmoy [this message]
2020-08-12 13:42   ` Alex Deucher
2020-08-12  4:56 ` [PATCH 4/4] drm/amd/powerplay: enable Sienna Cichlid " Evan Quan

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