From mboxrd@z Thu Jan  1 00:00:00 1970
From: Marek Vasut <marex@denx.de>
Date: Fri, 27 Apr 2018 16:37:42 +0200
Subject: [U-Boot] [PATCH v2] phy: add support for STM32 usb phy
	controller
In-Reply-To: <2fef8f01-812f-7580-80ed-0d1e9b9f8648@st.com>
References: <1524819715-23074-1-git-send-email-patrice.chotard@st.com>
 <0849b46f-a605-78fb-3264-df0e8ea07014@denx.de>
 <2fef8f01-812f-7580-80ed-0d1e9b9f8648@st.com>
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On 04/27/2018 04:28 PM, Patrice CHOTARD wrote:
> Hi Marek
> 
> On 04/27/2018 11:18 AM, Marek Vasut wrote:
>> On 04/27/2018 11:01 AM, Patrice Chotard wrote:
>>> This patch adds phy tranceiver driver for STM32 USB PHY
>>> Controller (usbphyc) that provides dual port High-Speed
>>> phy for OTG (single port) and EHCI/OHCI host controller
>>> (two ports).
>>
>> Oh, I see.
>>
>>> One port of the phy is shared between the two USB controllers
>>> through a UTMI+ switch.
>>>
>>> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
>>> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
>>> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
>>> ---
>>
>> [...]
>>
>>> +static int stm32_usbphyc_probe(struct udevice *dev)
>>> +{
>>> +	struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
>>> +	struct reset_ctl reset;
>>> +	ofnode node;
>>> +	int i, ret;
>>> +
>>> +	usbphyc->base = dev_read_addr(dev);
>>> +	if (usbphyc->base == FDT_ADDR_T_NONE)
>>> +		return -EINVAL;
>>> +
>>> +	/* Enable clock */
>>> +	ret = clk_get_by_index(dev, 0, &usbphyc->clk);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	ret = clk_enable(&usbphyc->clk);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	/* Reset */
>>> +	ret = reset_get_by_index(dev, 0, &reset);
>>> +	if (!ret) {
>>> +		reset_assert(&reset);
>>> +		udelay(2);
>>> +		reset_deassert(&reset);
>>
>> Shouldn't the reset delay be a reset controller property ?
> 
> There is no delay property in reset framework. The delay is more 
> dependent of the reseted IP than the reset controller.

OK, so be it.

-- 
Best regards,
Marek Vasut