From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: acme@redhat.com, mingo@kernel.org, linux-kernel@vger.kernel.org,
jolsa@kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com, ak@linux.intel.com
Subject: Re: [PATCH V6 07/14] perf/x86/intel: Generic support for hardware TopDown metrics
Date: Mon, 20 Jul 2020 14:11:54 -0400 [thread overview]
Message-ID: <c814c39a-3cd2-f4d3-0b89-fbe4993e1fcc@linux.intel.com> (raw)
In-Reply-To: <20200720174103.GV10769@hirez.programming.kicks-ass.net>
On 7/20/2020 1:41 PM, Peter Zijlstra wrote:
> On Fri, Jul 17, 2020 at 07:05:47AM -0700, kan.liang@linux.intel.com wrote:
>
>> For the event mapping, a special 0x00 event code is used, which is
>> reserved for fake events. The metric events start from umask 0x10.
>
>> +#define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)
>> +#define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0)
>> +#define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1)
>> +#define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2)
>> +#define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3)
>
> So this is internal and we can change it around if/when needed, right?
>
Yes
>> +#define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_BE_BOUND
>> +#define INTEL_PMC_MSK_TOPDOWN ((0xfull << INTEL_PMC_IDX_METRIC_BASE) | \
>> + INTEL_PMC_MSK_FIXED_SLOTS)
>> +
>> +/*
>> + * There is no event-code assigned to the TopDown events.
>> + *
>> + * For the slots event, use the pseudo code of the fixed counter 3.
>> + *
>> + * For the metric events, the pseudo event-code is 0x00.
>> + * The pseudo umask-code starts from 0x10.
>> + */
>> +#define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */
>> +/* Level 1 metrics */
>> +#define INTEL_TD_METRIC_RETIRING 0x1000 /* Retiring metric */
>> +#define INTEL_TD_METRIC_BAD_SPEC 0x1100 /* Bad speculation metric */
>> +#define INTEL_TD_METRIC_FE_BOUND 0x1200 /* FE bound metric */
>> +#define INTEL_TD_METRIC_BE_BOUND 0x1300 /* BE bound metric */
>> +#define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_BE_BOUND
>> +#define INTEL_TD_METRIC_NUM 4
>
> But this is ABI, once we merge this, it's stuck.
>
> Also, per how Fixed2 is 0x0300, should not Fixed16 (aka
> METRICS_RETIRING) be 0x1100 ?
>
> But aside of that, are we sure the hardware will never grow a Fixed16?
> Or do we want to be paranoid and move the metrics events up in the
> pseudo event space?
>
Right, we cannot guarantee that the number of fixed counters is always
less than 16.
I will move the metrics events to the middle of the pseudo event space.
+#define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */
+#define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */
+#define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */
+#define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */
Thanks,
Kan
next prev parent reply other threads:[~2020-07-20 18:11 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 14:05 [PATCH V6 00/14] TopDown metrics support for Icelake kan.liang
2020-07-17 14:05 ` [PATCH V6 01/14] perf/x86: Use event_base_rdpmc for the RDPMC userspace support kan.liang
2020-07-17 14:05 ` [PATCH V6 02/14] perf/x86/intel: Name the global status bit in NMI handler kan.liang
2020-07-17 14:05 ` [PATCH V6 03/14] perf/x86/intel: Introduce the fourth fixed counter kan.liang
2020-07-20 16:20 ` Peter Zijlstra
2020-07-20 18:22 ` Liang, Kan
2020-07-17 14:05 ` [PATCH V6 04/14] perf/x86/intel: Move BTS index to 47 kan.liang
2020-07-17 14:05 ` [PATCH V6 05/14] perf/x86/intel: Fix the name of perf METRICS kan.liang
2020-07-17 14:05 ` [PATCH V6 06/14] perf/x86/intel: Use switch in intel_pmu_disable/enable_event kan.liang
2020-07-20 16:22 ` Peter Zijlstra
2020-07-20 19:02 ` Liang, Kan
2020-07-17 14:05 ` [PATCH V6 07/14] perf/x86/intel: Generic support for hardware TopDown metrics kan.liang
2020-07-20 17:41 ` Peter Zijlstra
2020-07-20 18:11 ` Liang, Kan [this message]
2020-07-21 9:43 ` Peter Zijlstra
2020-07-21 14:05 ` Liang, Kan
2020-07-21 14:25 ` peterz
2020-07-17 14:05 ` [PATCH V6 08/14] perf/x86: Add a macro for RDPMC offset of fixed counters kan.liang
2020-07-17 14:05 ` [PATCH V6 09/14] perf/x86/intel: Support TopDown metrics on Ice Lake kan.liang
2020-07-21 12:40 ` Peter Zijlstra
2020-07-21 14:23 ` Liang, Kan
2020-07-21 14:31 ` peterz
2020-07-21 15:50 ` Liang, Kan
2020-07-21 17:38 ` Andi Kleen
2020-07-21 19:20 ` Peter Zijlstra
2020-07-17 14:05 ` [PATCH V6 10/14] perf/x86/intel: Support per-thread RDPMC TopDown metrics kan.liang
2020-07-17 14:05 ` [PATCH V6 11/14] perf/x86/intel: Disable sample-read the slots and metrics events kan.liang
2020-07-21 13:10 ` Peter Zijlstra
2020-07-21 16:07 ` Liang, Kan
2020-07-21 19:18 ` Peter Zijlstra
2020-07-22 19:26 ` Liang, Kan
2020-07-17 14:05 ` [PATCH V6 12/14] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2020-07-17 14:05 ` [PATCH V6 13/14] perf, tools, stat: Check Topdown Metric group kan.liang
2020-07-17 14:05 ` [PATCH V6 14/14] perf, tools: Add documentation for topdown metrics kan.liang
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