From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Sat, 9 Feb 2019 11:02:30 +0100 Subject: [U-Boot] [PATCH] arm: socfpga: move gen5 SDR driver to DM In-Reply-To: <70af5270f59aee8ed9f9786161ffb5193929cec5.camel@linux.intel.com> References: <20190207212309.27559-1-simon.k.r.goldschmidt@gmail.com> <70af5270f59aee8ed9f9786161ffb5193929cec5.camel@linux.intel.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 2/8/19 11:51 PM, Dalon L Westergreen wrote: > On Fri, 2019-02-08 at 21:36 +0100, Simon Goldschmidt wrote: >> >> >> Am Fr., 8. Feb. 2019, 21:28 hat Dalon L Westergreen < >> dalon.westergreen at linux.intel.com> geschrieben: >>> On Thu, 2019-02-07 at 22:23 +0100, Simon Goldschmidt wrote: >>>> To clean up reset handling for socfpga gen5, let's move the code snippet >>>> taking the DDR controller out of reset from SPL to the DDR driver. >>>> >>>> While at it, port the ddr driver to UCLASS_RAM and use dts. >>>> >>>> Signed-off-by: Simon Goldschmidt >>>> --- >>>> >>>> This is an RFC to show what the SDRAM driver moved to DM (UCLASS_RAM) >>> would >>>> look like. It's RFC both because Dinh did not seem too fond of changing >>> the >>>> register address of the SDR in devicetree to include what the undocumented >>>> registers 'sequencer.c' uses as well as because of my observed code >>> growth. >>>> >>>> Basically, I want to move this to UCLASS_RAM and I want to read the reset >>>> property for SDR from devicetree. What remains RFC is: do we want/need to >>>> read the base address from devicetree, or can we live with it being hard- >>>> coded (and maybe sanity-checked during probe)? >>>> >>> >>> My 2 cents, i love the idea of moving all of the socfgpa sdram code to DM. >>> Looking at the code, i would suggest that we should handle the case where >>> there is no HPS sdram controller, and instead an FPGA based controller is >>> used. Although not common, it is a use case i have seen repeatedly. >> >> While I haven't used it like that (I did use an FPGA RAM controller, but that >> was with a NIOS and not Linux, not HPS), I guess it should work with my >> changed. Just disable the 'sdr' node in the devicetree. You'll need a driver >> for the FPGA based RAM controller though. >> >> Or, in the setup you mentioned, would the existing driver be the same? I.e. >> just use a different base address? Or is it a different IP? > > All you need is to have the h2f bridge enabled during the boot. We used to do > this for you if spl found that the FPGA was already configured. On the FPGA > side, a nios in the ddr controller runs the ddr calibration code. This is stratix10 you're talking about, isn't it ? I recall S10 has nios2 hard block to start up the DRAM, but Gen5 and A10 do not have that, do they ? -- Best regards, Marek Vasut