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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH v4 41/45] target/arm: Enable FEAT_CSV2_2 for -cpu max Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20220501055028.646596-1-richard.henderson@linaro.org> <20220501055028.646596-42-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/3/22 10:10, Peter Maydell wrote: > On Sun, 1 May 2022 at 08:16, Richard Henderson > wrote: >> >> There is no branch prediction in TCG, therefore there is no >> need to actually include the context number into the predictor. >> Therefore all we need to do is add the state for SCXTNUM_ELx. >> >> Signed-off-by: Richard Henderson >> --- >> v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnum. >> v3: Rely on EL3-no-EL2 squashing during registration. >> --- >> docs/system/arm/emulation.rst | 3 ++ >> target/arm/cpu.h | 16 +++++++++ >> target/arm/cpu64.c | 3 +- >> target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- >> 4 files changed, 81 insertions(+), 2 deletions(-) > > Reviewed-by: Peter Maydell > > (The handling of SCXTNUM_EL0 should Just Work for user-mode-only, > right?) Hmm, interesting. The linux master does not support CSV2_1.2+. This bit is supposed to be RES1 when the feature is not enabled, so when booted with TCG at EL1 access *should* be trapped, when the guest kernel is not buggy. This falls into the /* ??? Lots of these bits are not implemented. */ fixme in sctlr_write. If the guest kernel is buggy... ya gets what ya gets. We are particularly sloppy with SCTLR_EL1 with user-only; the res1 bits are not set, which means that we'll expose the register at user-only. Although context swapping is not an issue for user-only, I think we should not expose the value at this time. It's plausible that the register will *never* be exposed to EL0. We might get, for instance, a prctl to set a new thread/process-level random value instead. Will provide a minimal user-only fix for v5, and work on sctlr_write another day. r~