From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C3F8C433EF for ; Wed, 8 Sep 2021 10:09:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5548960C51 for ; Wed, 8 Sep 2021 10:09:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5548960C51 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 653FF6E098; Wed, 8 Sep 2021 10:09:09 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1AEF6E098; Wed, 8 Sep 2021 10:09:08 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10100"; a="284149621" X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="284149621" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 03:09:08 -0700 X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="465463302" Received: from eoinwals-mobl.ger.corp.intel.com (HELO [10.213.233.175]) ([10.213.233.175]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 03:09:06 -0700 Subject: Re: [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers To: Matt Roper , intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Vinay Belgaumkar , Daniele Ceraolo Spurio , Aravind Iddamsetty References: <20210907171916.2548047-1-matthew.d.roper@intel.com> <20210907171916.2548047-4-matthew.d.roper@intel.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: Date: Wed, 8 Sep 2021 11:09:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210907171916.2548047-4-matthew.d.roper@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 07/09/2021 18:19, Matt Roper wrote: > Add execlists and GuC interrupts for compute CS into existing IRQ handlers. > > All compute command streamers belong to the same compute class, so the > only change needed to enable their interrupts is to program their GT engine > interrupt mask registers. > > CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one. > > BSpec: 50844, 54029, 54030, 53223, 53224. > Original-patch-by: Michel Thierry > Cc: Tvrtko Ursulin > Cc: Vinay Belgaumkar > Signed-off-by: Daniele Ceraolo Spurio > Signed-off-by: Aravind Iddamsetty > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++++++++++++++- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 3 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > index b2de83be4d97..612281d47513 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > @@ -96,7 +96,7 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) > if (unlikely(!intr)) > return; > > - if (class <= COPY_ENGINE_CLASS) > + if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS) > return gen11_engine_irq_handler(gt, class, instance, intr); > > if (class == OTHER_CLASS) > @@ -178,6 +178,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt) > /* Disable RCS, BCS, VCS and VECS class engines. */ > intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); > intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); > + if (CCS_MASK(gt)) > + intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); > > /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ > intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); > @@ -191,6 +193,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt) > intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0); > if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) > intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0); > + if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) > + intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); > + if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) > + intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); > > intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); > intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); > @@ -218,6 +224,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > /* Enable RCS, BCS, VCS and VECS class interrupts. */ > intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask); > intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); > + if (CCS_MASK(gt)) > + intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); > > /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ > intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); > @@ -231,6 +239,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask); > if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) > intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask); > + if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) > + intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); > + if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) > + intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); > + > /* > * RPS interrupts will get enabled/disabled on demand when RPS itself > * is enabled/disabled. > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1fd3040b6771..5b6eee5d8ade 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1573,6 +1573,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) > #define VEBOX_MASK(gt) \ > ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) > +#define CCS_MASK(gt) \ > + ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) > > /* > * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 33d6aa0b07c1..31e9c2cc4c0c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8139,6 +8139,7 @@ enum { > #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) > #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) > #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) > +#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048) > > #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) > #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) > @@ -8152,6 +8153,8 @@ enum { > #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) > #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) > #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) > +#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100) > +#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104) > > #define ENGINE1_MASK REG_GENMASK(31, 16) > #define ENGINE0_MASK REG_GENMASK(15, 0) > Reviewed-by: Tvrtko Ursulin Regards, Tvrtko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2A41C433FE for ; Wed, 8 Sep 2021 10:09:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B18B60C51 for ; Wed, 8 Sep 2021 10:09:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9B18B60C51 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EBA3A6E17E; Wed, 8 Sep 2021 10:09:09 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1AEF6E098; Wed, 8 Sep 2021 10:09:08 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10100"; a="284149621" X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="284149621" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 03:09:08 -0700 X-IronPort-AV: E=Sophos;i="5.85,277,1624345200"; d="scan'208";a="465463302" Received: from eoinwals-mobl.ger.corp.intel.com (HELO [10.213.233.175]) ([10.213.233.175]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2021 03:09:06 -0700 To: Matt Roper , intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, Vinay Belgaumkar , Daniele Ceraolo Spurio , Aravind Iddamsetty References: <20210907171916.2548047-1-matthew.d.roper@intel.com> <20210907171916.2548047-4-matthew.d.roper@intel.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: Date: Wed, 8 Sep 2021 11:09:05 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210907171916.2548047-4-matthew.d.roper@intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 07/09/2021 18:19, Matt Roper wrote: > Add execlists and GuC interrupts for compute CS into existing IRQ handlers. > > All compute command streamers belong to the same compute class, so the > only change needed to enable their interrupts is to program their GT engine > interrupt mask registers. > > CCS0 shares the register with CCS1, while CCS2 and CCS3 are in a new one. > > BSpec: 50844, 54029, 54030, 53223, 53224. > Original-patch-by: Michel Thierry > Cc: Tvrtko Ursulin > Cc: Vinay Belgaumkar > Signed-off-by: Daniele Ceraolo Spurio > Signed-off-by: Aravind Iddamsetty > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++++++++++++++- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 3 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > index b2de83be4d97..612281d47513 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > @@ -96,7 +96,7 @@ gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity) > if (unlikely(!intr)) > return; > > - if (class <= COPY_ENGINE_CLASS) > + if (class <= COPY_ENGINE_CLASS || class == COMPUTE_CLASS) > return gen11_engine_irq_handler(gt, class, instance, intr); > > if (class == OTHER_CLASS) > @@ -178,6 +178,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt) > /* Disable RCS, BCS, VCS and VECS class engines. */ > intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0); > intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0); > + if (CCS_MASK(gt)) > + intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0); > > /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ > intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0); > @@ -191,6 +193,10 @@ void gen11_gt_irq_reset(struct intel_gt *gt) > intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~0); > if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) > intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~0); > + if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) > + intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0); > + if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) > + intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0); > > intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); > intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); > @@ -218,6 +224,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > /* Enable RCS, BCS, VCS and VECS class interrupts. */ > intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask); > intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask); > + if (CCS_MASK(gt)) > + intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask); > > /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ > intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask); > @@ -231,6 +239,11 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask); > if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3)) > intel_uncore_write(uncore, GEN12_VECS2_VECS3_INTR_MASK, ~dmask); > + if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) > + intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask); > + if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3)) > + intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask); > + > /* > * RPS interrupts will get enabled/disabled on demand when RPS itself > * is enabled/disabled. > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1fd3040b6771..5b6eee5d8ade 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1573,6 +1573,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) > #define VEBOX_MASK(gt) \ > ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) > +#define CCS_MASK(gt) \ > + ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) > > /* > * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 33d6aa0b07c1..31e9c2cc4c0c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8139,6 +8139,7 @@ enum { > #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) > #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) > #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) > +#define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048) > > #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) > #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) > @@ -8152,6 +8153,8 @@ enum { > #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) > #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) > #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) > +#define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100) > +#define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104) > > #define ENGINE1_MASK REG_GENMASK(31, 16) > #define ENGINE0_MASK REG_GENMASK(15, 0) > Reviewed-by: Tvrtko Ursulin Regards, Tvrtko