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[201.43.103.101]) by smtp.gmail.com with ESMTPSA id bf17-20020a056808191100b0035173c2fddasm157040oib.51.2022.12.22.02.47.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Dec 2022 02:47:10 -0800 (PST) Message-ID: Date: Thu, 22 Dec 2022 07:47:06 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 01/15] tests/avocado: add RISC-V opensbi boot test Content-Language: en-US To: Bin Meng Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Cleber Rosa , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Wainer dos Santos Moschetta , Beraldo Leal References: <20221221182300.307900-1-dbarboza@ventanamicro.com> <20221221182300.307900-2-dbarboza@ventanamicro.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/22/22 07:24, Bin Meng wrote: > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza > wrote: >> This test is used to do a quick sanity check to ensure that we're able >> to run the existing QEMU FW image. >> >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | >> RISCV32_BIOS_BIN firmware with minimal options. >> >> Cc: Cleber Rosa >> Cc: Philippe Mathieu-Daudé >> Cc: Wainer dos Santos Moschetta >> Cc: Beraldo Leal >> Signed-off-by: Daniel Henrique Barboza >> --- >> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 65 insertions(+) >> create mode 100644 tests/avocado/riscv_opensbi.py >> >> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py >> new file mode 100644 >> index 0000000000..abc99ced30 >> --- /dev/null >> +++ b/tests/avocado/riscv_opensbi.py >> @@ -0,0 +1,65 @@ >> +# opensbi boot test for RISC-V machines >> +# >> +# Copyright (c) 2022, Ventana Micro >> +# >> +# This work is licensed under the terms of the GNU GPL, version 2 or >> +# later. See the COPYING file in the top-level directory. >> + >> +from avocado_qemu import QemuSystemTest >> +from avocado_qemu import wait_for_console_pattern >> + >> +class RiscvOpensbi(QemuSystemTest): >> + """ >> + :avocado: tags=accel:tcg >> + """ >> + timeout = 5 >> + >> + def test_riscv64_virt(self): >> + """ >> + :avocado: tags=arch:riscv64 >> + :avocado: tags=machine:virt >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >> + >> + def test_riscv64_spike(self): >> + """ >> + :avocado: tags=arch:riscv64 >> + :avocado: tags=machine:spike >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >> + >> + def test_riscv64_sifive_u(self): >> + """ >> + :avocado: tags=arch:riscv64 >> + :avocado: tags=machine:sifive_u >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >> + >> + def test_riscv32_virt(self): >> + """ >> + :avocado: tags=arch:riscv32 >> + :avocado: tags=machine:virt >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > How about testing riscv32_spike too? I didn't manage to make it work. This riscv64 spark command line boots opensbi: $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike OpenSBI v1.1    ____                    _____ ____ _____   / __ \                  / ____|  _ \_   _|  | |  | |_ __   ___ _ __ | (___ | |_) || |  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |  | |__| | |_) |  __/ | | |____) | |_) || |_   \____/| .__/ \___|_| |_|_____/|____/_____|         | |         |_| (...) The same command line doesn't boot riscv32 spark: ./qemu-system-riscv32 -nographic -display none -vga none -machine spike (--- hangs indefinitely ---) I debugged it a bit and, as far as boot code goes, it goes all the way and loads the opensbi 32bit binary. After that I tried to found any command line example that boots spike with riscv32 bit and didn't find any.  So I gave up digging it further because I became unsure about whether 32-bit spike works. If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's worth investigating why it's not the case ATM. Thanks, Daniel > >> + >> + def test_riscv32_sifive_u(self): >> + """ >> + :avocado: tags=arch:riscv32 >> + :avocado: tags=machine:sifive_u >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >> -- > Regards, > Bin