From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753662AbdDECgR (ORCPT ); Tue, 4 Apr 2017 22:36:17 -0400 Received: from mail.kmu-office.ch ([178.209.48.109]:50416 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752527AbdDECgP (ORCPT ); Tue, 4 Apr 2017 22:36:15 -0400 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Date: Tue, 04 Apr 2017 19:36:01 -0700 From: Stefan Agner To: Fabio Estevam Cc: Dong Aisheng , Shawn Guo , Sascha Hauer , Stephen Boyd , Dong Aisheng , Fabio Estevam , robh+dt@kernel.org, Mark Rutland , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel Subject: Re: [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances In-Reply-To: References: <20170330005029.6472-1-stefan@agner.ch> <20170330005029.6472-2-stefan@agner.ch> <20170401030312.GB24882@b29396-OptiPlex-7040> <5c8339900fa1bd6215fb94d4386f7e06@agner.ch> Message-ID: User-Agent: Roundcube Webmail/1.1.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2017-04-04 19:15, Fabio Estevam wrote: > On Sun, Apr 2, 2017 at 2:02 PM, Fabio Estevam wrote: >> On Sat, Apr 1, 2017 at 1:15 AM, Stefan Agner wrote: >> >>> IMX7D_IPG_ROOT_CLK is currently not a valid clock in upstream... So we >>> would have to add it to the clock driver first. >>> >>> I guess we could/should add it anyway at one point? But probably also as >>> init on, just to make sure Linux does not disable it since it is >>> currently used by several IPs implicitly. >> >> Yes, I made a previous attempt do add IMX7D_IPG_ROOT_CLK and it did >> not work as I did not put it in the init_on clock list. >> >> Will submit a new patch adding it to init_on, thanks. > > I thought that adding IMX7D_IPG_ROOT_CLK would do the trick, but the > patch below also causes the kernel to not boot: > > --- a/drivers/clk/imx/clk-imx7d.c > +++ b/drivers/clk/imx/clk-imx7d.c > @@ -386,7 +386,7 @@ static int const clks_init_on[] __initconst = { > IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK, > IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK, > IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK, > - IMX7D_AHB_CHANNEL_ROOT_CLK, > + IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK, > }; > > static struct clk_onecell_data clk_data; > @@ -788,7 +788,7 @@ static void __init imx7d_clocks_init(struct > device_node *ccm_node) > clks[IMX7D_WRCLK_ROOT_DIV] = > imx_clk_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, > 6); > clks[IMX7D_CLKO1_ROOT_DIV] = > imx_clk_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, > 6); > clks[IMX7D_CLKO2_ROOT_DIV] = > imx_clk_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, > 6); > - > + clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider2("ipg_root_clk", > "ahb_root_clk", base + 0x9080, 0, 2); > clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate4("arm_a7_root_clk", > "arm_a7_div", base + 0x4000, 0); > clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", > "arm_m4_div", base + 0x4010, 0); > clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate4("arm_m0_root_clk", > "arm_m0_div", base + 0x4020, 0); Hm, imx_clk_divider2 sets CLK_SET_RATE_PARENT, maybe that influences the parent? I guess we actually don't want the clock framework to change that clock rate, not sure whether we can freeze it or similar. -- Stefan From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Agner Subject: Re: [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances Date: Tue, 04 Apr 2017 19:36:01 -0700 Message-ID: References: <20170330005029.6472-1-stefan@agner.ch> <20170330005029.6472-2-stefan@agner.ch> <20170401030312.GB24882@b29396-OptiPlex-7040> <5c8339900fa1bd6215fb94d4386f7e06@agner.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Fabio Estevam Cc: Dong Aisheng , Shawn Guo , Sascha Hauer , Stephen Boyd , Dong Aisheng , Fabio Estevam , robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Mark Rutland , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel List-Id: devicetree@vger.kernel.org On 2017-04-04 19:15, Fabio Estevam wrote: > On Sun, Apr 2, 2017 at 2:02 PM, Fabio Estevam wrote: >> On Sat, Apr 1, 2017 at 1:15 AM, Stefan Agner wrote: >> >>> IMX7D_IPG_ROOT_CLK is currently not a valid clock in upstream... So we >>> would have to add it to the clock driver first. >>> >>> I guess we could/should add it anyway at one point? But probably also as >>> init on, just to make sure Linux does not disable it since it is >>> currently used by several IPs implicitly. >> >> Yes, I made a previous attempt do add IMX7D_IPG_ROOT_CLK and it did >> not work as I did not put it in the init_on clock list. >> >> Will submit a new patch adding it to init_on, thanks. > > I thought that adding IMX7D_IPG_ROOT_CLK would do the trick, but the > patch below also causes the kernel to not boot: > > --- a/drivers/clk/imx/clk-imx7d.c > +++ b/drivers/clk/imx/clk-imx7d.c > @@ -386,7 +386,7 @@ static int const clks_init_on[] __initconst = { > IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK, > IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK, > IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK, > - IMX7D_AHB_CHANNEL_ROOT_CLK, > + IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK, > }; > > static struct clk_onecell_data clk_data; > @@ -788,7 +788,7 @@ static void __init imx7d_clocks_init(struct > device_node *ccm_node) > clks[IMX7D_WRCLK_ROOT_DIV] = > imx_clk_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, > 6); > clks[IMX7D_CLKO1_ROOT_DIV] = > imx_clk_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, > 6); > clks[IMX7D_CLKO2_ROOT_DIV] = > imx_clk_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, > 6); > - > + clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider2("ipg_root_clk", > "ahb_root_clk", base + 0x9080, 0, 2); > clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate4("arm_a7_root_clk", > "arm_a7_div", base + 0x4000, 0); > clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", > "arm_m4_div", base + 0x4010, 0); > clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate4("arm_m0_root_clk", > "arm_m0_div", base + 0x4020, 0); Hm, imx_clk_divider2 sets CLK_SET_RATE_PARENT, maybe that influences the parent? I guess we actually don't want the clock framework to change that clock rate, not sure whether we can freeze it or similar. -- Stefan -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: stefan@agner.ch (Stefan Agner) Date: Tue, 04 Apr 2017 19:36:01 -0700 Subject: [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances In-Reply-To: References: <20170330005029.6472-1-stefan@agner.ch> <20170330005029.6472-2-stefan@agner.ch> <20170401030312.GB24882@b29396-OptiPlex-7040> <5c8339900fa1bd6215fb94d4386f7e06@agner.ch> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 2017-04-04 19:15, Fabio Estevam wrote: > On Sun, Apr 2, 2017 at 2:02 PM, Fabio Estevam wrote: >> On Sat, Apr 1, 2017 at 1:15 AM, Stefan Agner wrote: >> >>> IMX7D_IPG_ROOT_CLK is currently not a valid clock in upstream... So we >>> would have to add it to the clock driver first. >>> >>> I guess we could/should add it anyway at one point? But probably also as >>> init on, just to make sure Linux does not disable it since it is >>> currently used by several IPs implicitly. >> >> Yes, I made a previous attempt do add IMX7D_IPG_ROOT_CLK and it did >> not work as I did not put it in the init_on clock list. >> >> Will submit a new patch adding it to init_on, thanks. > > I thought that adding IMX7D_IPG_ROOT_CLK would do the trick, but the > patch below also causes the kernel to not boot: > > --- a/drivers/clk/imx/clk-imx7d.c > +++ b/drivers/clk/imx/clk-imx7d.c > @@ -386,7 +386,7 @@ static int const clks_init_on[] __initconst = { > IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK, > IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK, > IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK, > - IMX7D_AHB_CHANNEL_ROOT_CLK, > + IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK, > }; > > static struct clk_onecell_data clk_data; > @@ -788,7 +788,7 @@ static void __init imx7d_clocks_init(struct > device_node *ccm_node) > clks[IMX7D_WRCLK_ROOT_DIV] = > imx_clk_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, > 6); > clks[IMX7D_CLKO1_ROOT_DIV] = > imx_clk_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, > 6); > clks[IMX7D_CLKO2_ROOT_DIV] = > imx_clk_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, > 6); > - > + clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider2("ipg_root_clk", > "ahb_root_clk", base + 0x9080, 0, 2); > clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate4("arm_a7_root_clk", > "arm_a7_div", base + 0x4000, 0); > clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", > "arm_m4_div", base + 0x4010, 0); > clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate4("arm_m0_root_clk", > "arm_m0_div", base + 0x4020, 0); Hm, imx_clk_divider2 sets CLK_SET_RATE_PARENT, maybe that influences the parent? I guess we actually don't want the clock framework to change that clock rate, not sure whether we can freeze it or similar. -- Stefan