[MODERATED] AMD SSBD extension document

[MODERATED] AMD SSBD extension document

[Tom Lendacky]

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I'm including the documentation on the AMD SSBD extension support.
This is preliminary information, please share only as needed.

Thanks,
Tom

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[MODERATED] Re: AMD SSBD extension document

[Alexei Starovoitov]

On Fri, May 18, 2018 at 10:26:46AM -0500, speck for Tom Lendacky wrote:
> I'm including the documentation on the AMD SSBD extension support.
> This is preliminary information, please share only as needed.

thanks a lot of the doc!

Could you share what cases of memory disambiguation are being disabled,
so we can better estimate the impact ?

Same question to Intel folks.

Like, does it disable store-to-load forwarding out of store queue as well?
Meaning that today push+pop is a single cycle operation and passing
more than 5 arguments to functions via stack is still fast.
Callee saving registers with a sequence of pushes and pops is fast too.
If that is being disabled my MSR, it would mean that any short function
that has small number of insns to execute will be penalized with
save/restore of registers. The functions with more than 5 args will see
the penalty too.
The ubiquitous register spill/fill is penalized as well?

[MODERATED] Re: AMD SSBD extension document

[Linus Torvalds]

On Fri, 18 May 2018, speck for Alexei Starovoitov wrote:
> 
> Like, does it disable store-to-load forwarding out of store queue as well?

It really shouldn't, and based on the (limited) performance data I've seen 
I don't think it does.

Afaik it only disabled the speculative case of reading the data early when 
a previous store hasn't even entered the store buffer yet because the 
store address isn't known.

So it's actually the exact reverse of your worry - the bug is that CPU's 
will *not* snoop the store buffer (or snoop an even earlier wrong entry in 
the store buffer), because they'll try to do the read speculatively early.

               Linus