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From: Richard Henderson <richard.henderson@linaro.org>
To: Lijun Pan <ljp@linux.ibm.com>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	david@gibson.dropbear.id.au
Subject: Re: [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions
Date: Fri, 24 Jul 2020 11:00:39 -0700	[thread overview]
Message-ID: <ca98ae77-d5db-7e22-5cfc-fb855d79fed5@linaro.org> (raw)
In-Reply-To: <20200724045845.89976-7-ljp@linux.ibm.com>

On 7/23/20 9:58 PM, Lijun Pan wrote:
> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo
> VA-form.
> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned
> Doubleword VA-form.
> 
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> v5: update instruction flag for vmsumcud.
>     integrate into this isa3.1 patch series
> v3: implement vmsumudm/vmsumcud through int128 functions,
>     suggested by Richard Henderson.
> 
>  disas/ppc.c                         |  2 ++
>  target/ppc/helper.h                 |  4 ++-
>  target/ppc/int_helper.c             | 49 ++++++++++++++++++++++++++++-
>  target/ppc/translate.c              |  1 -
>  target/ppc/translate/vmx-impl.inc.c | 39 ++++++++++++-----------
>  target/ppc/translate/vmx-ops.inc.c  |  2 ++
>  6 files changed, 76 insertions(+), 21 deletions(-)
> 
> diff --git a/disas/ppc.c b/disas/ppc.c
> index 63e97cfe1d..bd76fae4c4 100644
> --- a/disas/ppc.c
> +++ b/disas/ppc.c
> @@ -2261,7 +2261,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  { "vmsumshs",  VXA(4,  41), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
>  { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
>  { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
> +{ "vmsumudm",  VXA(4,  35), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
>  { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
> +{ "vmsumcud",  VXA(4,  23), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
>  { "vmulesb",   VX(4,  776), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
>  { "vmulesh",   VX(4,  840), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
>  { "vmuleub",   VX(4,  520), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 70a14029ca..00a31d64bc 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -274,10 +274,12 @@ DEF_HELPER_3(vpkpx, void, avr, avr, avr)
>  DEF_HELPER_5(vmhaddshs, void, env, avr, avr, avr, avr)
>  DEF_HELPER_5(vmhraddshs, void, env, avr, avr, avr, avr)
>  DEF_HELPER_5(vmsumuhm, void, env, avr, avr, avr, avr)
> +DEF_HELPER_5(vmsumudm, void, env, avr, avr, avr, avr)
>  DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr)
>  DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr)
>  DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr)
> -DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr)
> +DEF_HELPER_5(vmsumcud, void, env, avr, avr, avr, avr)
> +DEF_HELPER_5(vmladduhm, void, env, avr, avr, avr, avr)
>  DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32)
>  DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env)
>  DEF_HELPER_3(lvebx, void, env, avr, tl)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index 62b93b4568..2e919a7b8e 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -913,7 +913,8 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
>      }
>  }
>  
> -void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +void helper_vmladduhm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
> +                      ppc_avr_t *b, ppc_avr_t *c)

Why?

> +void helper_vmsumudm(CPUPPCState *env, ppc_avr_t *r,
> +                     ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> +{

...

> +void helper_vmsumcud(CPUPPCState *env, ppc_avr_t *r,
> +                     ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)

You don't actually use env in either helper, so you shouldn't pass it in.


r~


  reply	other threads:[~2020-07-24 18:02 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-24  4:58 [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-24  4:58 ` [PATCH v5 1/6] Update PowerPC AT_HWCAP2 definition Lijun Pan
2020-07-24 17:54   ` Richard Henderson
2020-07-24  4:58 ` [PATCH v5 2/6] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
2020-07-24 17:56   ` Richard Henderson
2020-07-24  4:58 ` [PATCH v5 3/6] target/ppc: add vmulh{su}w instructions Lijun Pan
2020-07-24 17:57   ` Richard Henderson
2020-07-27  6:32     ` David Gibson
2020-07-24  4:58 ` [PATCH v5 4/6] target/ppc: add vmulh{su}d instructions Lijun Pan
2020-07-24  4:58 ` [PATCH v5 5/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Lijun Pan
2020-07-24  4:58 ` [PATCH v5 6/6] target/ppc: add vmsumudm vmsumcud instructions Lijun Pan
2020-07-24 18:00   ` Richard Henderson [this message]
2020-07-24 18:46     ` Lijun Pan
2020-07-24 23:07       ` Lijun Pan
2020-07-27  6:33 ` [PATCH v5 0/6] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson

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