On 25/06/2018 18:32, speck for Dave Hansen wrote:
> On 06/25/2018 07:26 AM, speck for Paolo Bonzini wrote:
>> On 23/06/2018 15:54, speck for konrad.wilk_at_oracle.com wrote:
>>> +	if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
>>> +		wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
>>> +		return;
>>> +	}
>>> +
>>> +	/* FIXME: could this be boot_cpu_data.x86_cache_size * 2?  */
>>> +	size = PAGE_SIZE << L1D_CACHE_ORDER;
>> Regarding this "FIXME": Peter or Tim, do you know if loading 32KiB is
>> enough on pre-Skylake parts to clear the L1D cache?
> 
> As usual, it's complicated.
> 
> 32k is theoretically enough, but _only_ if none of the lines being
> touched were in the cache previously.  That's why it was a 64k buffer in
> some examples.

But pre-Skylake has 16k cache only, doesn't it?  Does it need to read in
4 times the cache size?

> You also need guard pages at either end to ensure the prefetchers don't
> run into the next page.

Hmm, it would be a pity to require order 5 even.  Earlier in the thread
someone said that 52 KiB were enough, if that's confirmed we could keep
order 4 and have guard pages.

Paolo